IP Cores

I'm investigating wrapping standard Xilinx primitives inside the MPD/PAO structure required to include them in EDK projects.  Unzip them, and place them in the "pcores" subdirectory of your EDK project folder.

My first attempt is a simple parameterised wrapper around the DCM (Digital Clock Manager).  Parameters are the clock multiplier and divisor factors, and the input clock period (specified in nanoseconds).  Optionally the wrapper will instantiate BUFG components on the input and/or output clock signals.  I haven't tested this bit yet, so please send me feedback if it works or doesn't work for you.