Research Report - 2001
Digital Systems
Academic Staff
Dr Adam Postula
Prof Neil Bergmann
Dr Peter Sutton
Research Students
Mr Vince Boros
Mr Mark Calder
Mr Song Chen
Mr Ian Field
Mr Tony Han
Mr Simon Leung
Mr Kenny Lin
Mr Li-Yang Lin
Mr Pradeep Prabhakaran
Mr Allan Rae
Mr Anup Raghavan
Mr Kamal Rajagopalan
Miss Montserrat Ros
Mr Kenneth Siu
Mr Wing-Fai Wong
Contact Details
Prof Neil Bergmann
Email: bergmann@csee.uq.edu.au
Tel: 3365 1182
Dr Adam Postula
Email: adam@csee.uq.edu.au
Tel: 3365 3746
Dr Peter Sutton
Email: p.sutton@csee.uq.edu.au
Tel: 3365 4854
Our school’s research addresses two major problems of digital system design:
Reducing the design time of complex digital systems
Reducing the time required to execute computational tasks
Reducing the design time of complex systems has become one of the most urgent problems in digital design practice and research. Electronic products have grown tremendously in complexity and there is a constant demand for new and more advanced products. Computer tools for automation of lower level hardware design tasks are commercially available but there is a growing demand for automatic conversion of functional and behavioural specifications to working hardware. This would not only allow a designer to delegate the tedious and error prone tasks to a computer but also to concentrate on the system design and experiment with different system solutions. This area is targeted by staff and students working on automatic synthesis of hardware from behavioural specification. The main problems studied are synthesis of memory configurations and pipelining of operations that lead to better performance.
The hardware is only a part of a digital system. The software is often as demanding and as crucial to the system performance as hardware. The most important design decisions are made by designers when the system is partitioned into hardware and software parts. At present, designers do not have much support in this difficult task and there is a growing demand for automated or interactive tools supporting partitioning, performance estimation and performance optimisation. Hardware-software codesign research in this department is focused on the development of methods and tools allowing designers to optimise interaction of hardware and software into their designs.
Modern computers are becoming more and more powerful but there is always many problems which could be executed more quickly than a general purpose computer is currently able to do. In fact, the demand for computing performance in scientific computations and optimisation of designs in different fields of engineering is outgrowing the rate of performance improvement of general purpose computers. There are many computational tasks that arise so frequently that it is worthwhile considering the development of special purpose computers designed to execute such tasks. Special purpose architectures can provide the highest speeds of all (for a given cost ) and the development of those architectures is a rapidly growing area. Special computer architectures combined with reprogramming capability of Field Programmable Gate Arrays allow for a new way of tackling complex computational problems. A future computer can be viewed as a reconfigurable interconnection of specialised processors optimised for specific, although often executed, tasks. The research in this department is concentrated on the architectural and software issues of specialised computers.
Another approach to the reduction of computation time which is being investigated in our school is rather more fundamental and concerns the study of the basic computational devices themselves (e.g. MOSFET transistors). A number of investigations are underway which are aimed at gaining a greater understanding of both the fabrication process and the operational behaviour of semiconductor devices employed in computational systems. Such research leads to improving both the materials and technological processes and as a result improving the performance of computational devices.
Architectures for Reconfigurable System-on-Chip (RsoCs).
Custom Computers or Reconfigurable Computers consist of a processor which can execute conventional control-flow software programs plus uncommitted logic gates which can implement algorithms as data-flow hardware circuits. The combination of these two technologies provides a powerful new programming paradigm. When both processor & FPGA are included on a single chip we have a Reconfigurable System-on-Chip. These chips are available from manufacturers such as Atmel, Xilinx, Altera and Triscend. This project explores how to design and implement technologies using such chips.
RSoC support for Real-Time Applications
Real-time systems require responses which are both functionally correct and occur at the correct time. Reconfigurable System-on-Chip technology enables time-critical elements of an algorithm to be implemented as hardware circuits giving considerably more deterministic times for responses. This project investigates how real-time programs can be aided by the use of RSoC, and how time time-critical components can be identified and automatically compiled into hardware.
Adaptive Instrument Module for Low-Earth Orbit Satellite.
Australia’s Cooperative Research Centre for Satellite Systems (CRCSS) is launching the world’s first reconfigurable computer in space in 2002. This project, jointly with CRCSS, explores the use of this reconfigurable computer for adaptive instrument interfacing for low-earth orbit satellites, and also investigates the additional problems of using a reconfigurable computer in such a satellite.
RSoC support for Java Virtual Machines
There is now keen interest in Java as a programming language for networked embedded systems and intelligent appliances. Java programs are stored as Java bytecode, which is effectively machine code for a Java virtual machine. There are three models for executing JVMs on a real processor– an interpreter, a Just-in-Time compiler to real machine code, or a processor which directly executes Java bytecode. This project investigates how all three of these execution models could be improved by the use of additional hardware circuits implemented on an RSoC.
RSoC support for .NET Intermediate Code.
Similar to Java, Microsoft’s new .NET framework includes a common intermediate bytecode. In a similar fashion to the “RSoC support for Java Virtual Machines” project, this project investigates how execution of this code could be improved by the use of additional hardware circuits implemented on an RSoC.
JPad – A Java-based Embedded System Platform.
This project aims to build a modular embedded system prototyping system, consisting of PCB cards such as processor module (with RSoC-based processor), networking modules, display and interface modules, and sensors and actuator modules. This project investigates the design and evaluation of such a system based on the Java programming language.
Home Automation Networks based on Jini
Jini is SUN’s plug-and-play networking standard which allows devices connected to a network to be automatically configured, to publish their capabilities to other devices, and to access resources from other networked components. This project investigates how Jini can be used as the basis for low-cost, self-configuring networks of intelligent domestic appliances.
Home Automation Networks based on UPnP
Universal Plug n Play is Microsoft’s plug-and-play networking standard which allows devices connected to a network to be automatically configured, to publish their capabilities to other devices, and to access resources from other networked components. This project investigates how uPnP can be used as the basis for low-cost, self-configuring networks of intelligent domestic appliances.
Custom Computing Machines
A Custom Computing Machine (CCM) is highly optimised for a particular class of algorithms and can outperform a supercomputer in execution of those programs. Field Programmable Circuits help to make such computing machines flexible and reconfigurable. Design of such machines requires a great deal of expertise and is a complex and time consuming task. This project researches different principles of building CCMs automatically. The focus is on finding ways to parallelise computations in such a way that the required performance is attained with minimal cost of hardware and design effort.
Automatic Synthesis of Specialised Memory Systems for Custom Computing Machines
It has been observed that memory access is the main bottleneck in the ordinary computers as well as in the specially built computing machines. One way of improving the access time is to parallelise the memories. Then there is a number of problems to be solved regarding optimal structures of memories providing conflict free access for particular data structures in the algorithm to be executed. This project focuses on finding automatically such schemes and optimising the whole interleaved memory system regarding the cost and performance. The results of this research are applicable not only in custom computing but also in telecommunication problems where data access must be parallelise for easy data manipulation.
Specialised Programmable Architecture for Telecommunication Applications
New generations of Field Programmable Gate Arrays have reached a size of one million gates and have included memory cells. They have a flexible architecture for mapping many different types of algorithms for execution. However, their performance has suffered heavily in order to provide for flexibility. On the other hand, custom hardware circuits are small, fast and low power. However, they do suffer from lack of flexibility, long development cycle and no (or very limited) reconfigurability. Another feature of telecommunication applications is that the data flow path is very clearly defined. This is a characteristic which should be utilised during circuit implementation to achieve high performance, low power and silicon area efficiency. Our work is based on a semi-customised circuit design methodology. We are developing flexible hardware blocks based on customised circuit targeted directly for the functions used in baseband telecommunication. These blocks can be reconfigured to accommodate different standards. By discarding general functions not needed and using tailored-design circuits, performance and efficiency can be improved. Other research issues, such as reconfigurability of the structure regarding control, configuration, memory requirement and efficient interconnection system, are also investigated. The expected outcome of this project is telecommunication circuits which accepts many common standards used in the world while keeping complexity, silicon size and power consumption to much less of a general processor or a DSP processor. Another outcome of this work will be a simulation of GSM baseband processing using this new architecture.
The Use of a New System Description Language and its Application to Telecommunication
The use of a new system description language has the potential to allow for a rapid prototyping system. This is especially important in telecom- munication application because new standards emerge very quickly. The system has to be updated all the time, but extensive reliability testing is needed for each update. Hence, it is very important to shorten development cycle. In this investigation, the effect of using this new system description language on telecommunication circuits will be reported and documented. Specialised Programmable Hardware Architecture with Tailored CAD System for Efficient Circuit Mapping The fine-grain reconfigurable structure provided by Field Programmable Gate Arrays constitutes a very flexible platform circuit mapping and synthesis. Still, they provide only very general logic and memory resources, and lack such dedicated computing structures as ALUs, simple processors etc. Realisation of such module from fine-grain structure is slow and inefficient. This project focuses on finding ways to embed dedicated computing and data manipulation blocks into a FPGA-liked structure to achieve improvements. The architectural research will include issues such as reconfigurability regarding data path and control path, efficient interconnection system for the computing resources and memories. The expected outcome of this project is a FPGA-like architecture with flexible blocks suitable for building powerful reconfigurable machines for computing and data manipulation with a clear data flow, e.g. for use in telecommunication applications. A new CAD system will also need to be developed to cater for the new design possibilities created with this new architecture.
Automatic Synthesis of Analog Circuits from Behavioural Descriptions
Automatic synthesis of digital circuits has left research labs and is already an accepted industrial practice. The synthesis of analog circuitry is much more difficult and is still in its infancy but the demand for methods and tools is growing tremendously since the technological advances make it possible to implement very complex analog circuits. The aim of this project is to investigate both theoretical principles and practical aspects of synthe- sis from behavioural descriptions of analog functions. This is especially important since advanced simulation languages such as Analog VHDL and Analog Verilog will inevitably make inroads into industrial practice and will cause demand for automatic synthesis from behavioural descriptions.
Non-Fourier Transforms in Application to Pattern Comparison
Non-Fourier transforms based on integrals of Walsh functions provide some interesting opportunities for computationally efficient and accurate comparison of a pattern with a template. This project is focused on the theoretical and practical aspects of non-Fourier transforms applied to pattern recognition. In the theoretical part a system of piece-wise linear Walsh based functions is being developed that provides accurate (and very computationally effective) approximation of complex surfaces and volumes. A specialised computer based measurement system will be later built to apply the theoretical results.
Heterogeneous Processor Synthesis for Performance and Power
As we move towards larger and larger chips, these chips will contain several processors and memory on a single wafer. To automatically synthesise such a chip for application to a specific circuit requires the scheduling of tasks, allocation of tasks to processors, and the storing of code and data in appropriate memory elements for improving performance. Such circuits are also power hungry and it is imperative that the power in such circuits is reduced to the lowest possible amount. In this project a differential evolution method is used to schedule, allocate and reduce power.
Optical Interconnect Synthesis for Heterogeneous Processors
One of the significant bottlenecks in performance in the heterogeneous architectures is the interface between several processors. Electrical interconnects increase in delay as the feature size reduces. In this project we propose to use free space optical interconnect to improve performance. The optical circuits will be embedded in the silicon and is expected to provide a throughput several times that of the electrical interconnect.
Automated Sensor Interface Circuit Synthesis for Microprocessors
Sensors are an important part of any embedded system design. In this project we automatically create the analog circuits which are needed for the interfacing of the microprocessor to the sensor.
Automated Actuator Interface Circuit Synthesis for Microprocessors
One aspect in the design of embedded systems is the actuator driver. In this project an automated synthesis system for the actuator interface circuit design is being created. The system automatically creates an analog/digital circuit which will select the D/A converter, find the necessary circuit and then will find the necessary components to reduce cost, error and power.
Mixed Signal VLSI Circuit Synthesis
The improvements in VLSI technology has seen ever increasing wafer sizes and ever decreasing feature sizes. The extra wafer sizes can be used for increased digital functionality or to add analog circuitry. In his project we add analog circuitry to digital circuitry. The complete circuit is used to miniaturise a commercial circuit board.
Network Layer Converter Synthesis
Due to the differing networking standards employed, it is necessary to convert between standards. In this project an automated system is employed to create the network layer converter. The system takes the input and output packet profile and automatically synthesises a hardware circuit, which automatically converts from one network layer to another. The system also calculates the size and the speed of the circuit.
Hybrid FPGA Architecture for Reconfigurable Computing
Reconfigurable computing is the ability to modify computer hardware architecture in real time. At the heart of reconfigurable computers are devices call field programmable gate arrays (FPGAs). There are many different FPGA device architectures in existence from vendors such as Silinx, Altera and Actel. Different FPGA architectures are suited to different applications and some are more suited to reconfigurable computing than others. The aim of this research is to identify FPGA architecture features that best support reconfigurable computing and to design and simulate a new architecture that incorporates those features.
Place and Route for Partial FPGA Reconfiguration
One of the issues impacting the uptake of FPGA-based reconfigurable computing is the efficiency of the configuration creation process. The mapping of a configuration design to the underlying hardware architecture (the place and route process) is often time consuming for a complex design. Existing FPGA vendor place and route tools are, in general, designed for general purpose FPGA configuration design (where the length of the place and route process is not critical). Also, existing vendor tools do not provide much support for partial and dynamic reconfiguration. This project intends to develop CAD algorithms and subsequently a tool, which performs the place and route process for a partially reconfigurable system. Intially, the tool will target a particular type of FPGA - the Xilinx Virtex family. The Virtex family supports partial reconfiguration on a column by column basis. The implemented algorithms will be assessed to evaluate their performance.
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