/* * Driver for Zarlink DVB-T MT352 demodulator * * Written by Holger Waechtler * and Daniel Mack * * AVerMedia AVerTV DVB-T 771 support by * Wolfram Joost * * DVICO DVB-T support by * Chris Pascoe * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= */ #include #include #include #include #include "dvb_frontend.h" #define mt352_write(ibuf, ilen) \ do { \ struct i2c_msg msg = { .addr = card_type->mt352_i2c_addr, \ .flags = 0, .buf = ibuf, .len = ilen }; \ int err = i2c->xfer(i2c, &msg, 1); \ if (err != 1) { \ printk(KERN_WARNING \ "mt352_write() failed (err = %d)!\n", err); \ return err; \ } \ } while (0) #define msb(x) (((x) >> 8) & 0xff) #define lsb(x) ((x) & 0xff) #define FTT_FORCE_STEPSIZE_62500 0x01 /* For future use with "scan" function */ #define FTT_FORCE_STEPSIZE_166667 0x02 /* For future use with "scan" function */ #define FTT_CALC_FREQ_ONLY 0x04 /* For future use with "scan" function */ #define TTF_ASSUME_STEPSIZE_62500 0x01 /* For future use with "scan" function */ #define TTF_ASSUME_STEPSIZE_166667 0x02 /* For future use with "scan" function */ typedef void (*freq_to_tuner_func)(u32 freq, u8 *regs, u32 opts); typedef u32 (*tuner_to_freq_func)(u8 *regs, u32 opts); typedef void (*tuner_init_func)(struct dvb_i2c_bus *i2c); /* * The LG Z201 gives us both 62500 and 166667 kHz steps. Pick * the size that gives us the lowest frequency offset. */ static void lgz201_freq_to_tuner(u32 freq, u8 *tuner_regs, u32 opts) { u32 if_freq = freq + 36166667; u16 tmp; u8 rs; if ((!(opts & FTT_FORCE_STEPSIZE_62500)) && ((opts & FTT_FORCE_STEPSIZE_166667) || ((if_freq % 83333) < (if_freq % 31250)))) { /* Set divider == RSA /RSB (166667Hz step) */ rs = 0x04; if_freq += 83333; if_freq /= 1000; tmp = (6 * if_freq) / 1000; } else { /* Set divider == RSA RSB (62500Hz step) */ rs = 0x06; if_freq += 31250; if_freq /= 1000; tmp = (16 * if_freq) / 1000; } tuner_regs[0] = msb(tmp); tuner_regs[1] = lsb(tmp); if (opts & FTT_CALC_FREQ_ONLY) return; if (freq < 542000000) tuner_regs[2] = 0xB8 | rs; /* CONT_1, charge pump byte */ /* 125uA */ else if (freq < 830000000) tuner_regs[2] = 0xF0 | rs; /* 250uA */ else tuner_regs[2] = 0xF8 | rs; /* 650uA */ /* * TUA6034 recommended band frequencies: * + LOW: 48.25 - 154.25 MHz * + MID: 161.25 - 439.25 MHz * + HIGH: 447.25 - 863.25 MHz */ /* Bandswitch byte: * + VHF LOW band mixer/osc if (/P1 P0), not supported on this tuner * + VHF MID band mixer/osc if ( P1 /P0) * + UHF HIGH band mixer/osc if (/P1 /P0) * + Stand-by mode if ( P1 P0) */ /* As recommended by LG: */ if (freq == 0) tuner_regs[3] = 0x03; /* Standby */ else if (freq < 157500000) tuner_regs[3] = 0x01; /* LOW band, not used for DVB-T */ else if (freq < 443250000) tuner_regs[3] = 0x02; /* MID band */ else { tuner_regs[3] = 0x04; /* HIGH band */ #if IN_GERMANY tuner_regs[3] |= 0x08; /* Activate IF SAW filter */ #endif } } static u32 lgz201_tuner_to_freq(u8 *tuner_regs, u32 opts) { u16 tmp; /* Calculate freq in Hz. If we aren't given a forced * stepsize, then assume the tuner control word follows * and determine the stepsize from it. */ tmp = (tuner_regs[0] << 8) | tuner_regs[1]; if ((!(opts & TTF_ASSUME_STEPSIZE_166667)) && ((opts & TTF_ASSUME_STEPSIZE_62500) || (tuner_regs[2] & 0x02))) return (tmp * 62500) - 36166667; else return (tmp * 166667) - 36166667; } static void default_freq_to_tuner(u32 freq, u8 *tuner_regs, u32 opts) { u16 tmp; /* here we assume 1/6MHz == 166.66kHz stepsize */ #define IF_FREQUENCYx6 217 /* 6 * 36.16666666667MHz */ freq /= 1000; tmp = (3 * freq) / 500 + IF_FREQUENCYx6; tuner_regs[0] = msb(tmp); /* CHAN_START_(1|0) */ tuner_regs[1] = lsb(tmp); if (opts & FTT_CALC_FREQ_ONLY) return; /* Default tuner routine */ printk(KERN_WARNING "buf9,10: %02x %02x\n", tuner_regs[0], tuner_regs[1]); if (freq < 542000) tuner_regs[2] = 0xBE; /* CONT_1, charge pump byte */ else if (freq < 830000) tuner_regs[2] = 0xF6; else tuner_regs[2] = 0xFE; if (freq < 250000) /* VHF, freq < 250MHz */ tuner_regs[3] = 0x01; /* CONT_0, bandswitch byte */ else tuner_regs[3] = 0x08; } static u32 default_tuner_to_freq(u8 *tuner_regs, u32 opts) { u16 div; div = (tuner_regs[0] << 8) | tuner_regs[1]; return (500 * (div - IF_FREQUENCYx6) ) / 3 * 1000; } static void avermedia771_freq_to_tuner(u32 freq, u8 *tuner_regs, u32 opts) { default_freq_to_tuner(freq, tuner_regs, opts | FTT_CALC_FREQ_ONLY); if (opts & FTT_CALC_FREQ_ONLY) return; freq /= 1000; if (freq < 150000) { tuner_regs[2] = 0xB4; tuner_regs[3] = 0x01; } else if (freq < 173000) { tuner_regs[2] = 0xBC; tuner_regs[3] = 0x01; } else if (freq < 250000) { tuner_regs[2] = 0xB4; tuner_regs[3] = 0x02; } else if (freq < 400000) { tuner_regs[2] = 0xBC; tuner_regs[3] = 0x02; } else if (freq < 420000) { tuner_regs[2] = 0xF4; tuner_regs[3] = 0x02; } else if (freq < 470000) { tuner_regs[2] = 0xFC; tuner_regs[3] = 0x02; } else if (freq < 600000) { tuner_regs[2] = 0xBC; tuner_regs[3] = 0x08; } else if (freq < 730000) { tuner_regs[2] = 0xF4; tuner_regs[3] = 0x08; } else { tuner_regs[2] = 0xFC; tuner_regs[3] = 0x08; } } struct i2c_init_msg { u8 buflen:7; /* buffer length */ u8 delay_after:1; /* delay after message */ u8 i2c_buf[12]; /* i2c message */ }; /* * Card parameters and tuner specific functions */ static struct mt352_card_type { char *name; u8 pciid[4]; struct dvb_frontend_info *fe_info; u8 eeprom_i2c_addr; u8 eeprom_pciid_base; u8 mt352_i2c_addr; u8 tuner_i2c_addr; u8 mt352_input_freq[2]; /* INPUT_FREQ(1|0), see MT352 design manual p. 32 */ u8 mt352_trl_nominal_8mhz[2]; /* TRL_NOMINAL_RATE_(1|0), see MT352 design manual p. 33 */ u8 mt352_trl_nominal_7mhz[2]; u8 mt352_trl_nominal_6mhz[2]; struct i2c_init_msg init_routine[4]; /* I2C messages to initialize hardware */ u32 frequency_stepsize; freq_to_tuner_func freq_to_tuner; /* Converts frequency to tuner regs */ tuner_to_freq_func tuner_to_freq; /* Converts regs to tuner frequency */ } cardlist[] = { { "DVICO FusionHDTV DVB-T1", { 0xAC, 0x18, 0x00, 0xDB }, NULL, 0x50, 0x04, 0x0F, 0xC2, { 0x31, 0x05 }, { 0x72, 0x49 }, { 0x64, 0x00 }, { 0x55, 0xB7 }, { { 2, 0, { 0x8A, 0x39 } }, /* Parameters from LG */ { 3, 0, { 0x67, 0x24, 0x20 } }, /* AGC */ { 2, 0, { 0x8C, 0x33 } }, /* General purpose ports */ { 0 } }, 31250, lgz201_freq_to_tuner, lgz201_tuner_to_freq, }, { "AverMedia DVB-T 771", { 0x07, 0x71, 0x14, 0x61 }, NULL, 0x50, 0xFC, 0x0F, 0xC2, { 0x31, 0x05 }, { 0x72, 0x49 }, { 0x64, 0x00 }, { 0x55, 0xB7 }, { { 11, 1, { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x40, 0x40 } }, /* AGC */ { 2, 0, { 0xB5, 0x7A } }, /* ? Reserved register ? */ { 0 } }, 83333, avermedia771_freq_to_tuner, default_tuner_to_freq, }, { "Unknown Zarlink MT352-based DVB-T card", { }, NULL, 0xFF, 0xFF, 0x0F, 0xC2, { 0x31, 0x05 }, { 0x72, 0x49 }, { 0x64, 0x00 }, { 0x55, 0xB7 }, { { 3, 0, { 0x67, 0x19, 0xA0 } }, /* AGC */ { 0 } }, 166667, default_freq_to_tuner, default_tuner_to_freq }, }; #define NCARDS (sizeof(cardlist) / sizeof(struct mt352_card_type)) static struct dvb_frontend_info mt352_info_template = { .name = "DVB-T Zarlink MT352 demodulator driver", .type = FE_OFDM, .frequency_min = 174000000, /* NIM of AV771 starts at 50MHz */ .frequency_max = 862000000, .frequency_stepsize = 83333, /* .frequency_tolerance = 0, .symbol_rate_min = 1000000, .symbol_rate_max = 45000000, .symbol_rate_tolerance = ???, */ .notifier_delay = 0, .caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS }; int mt352_init (struct dvb_i2c_bus *i2c, struct mt352_card_type *card_type) { /** * all register write sequence have the register address of the * first register in the first byte, thenafter the value to write * into this and the following registers. */ static u8 mt352_reset [] = { 0x50, 0x80 }; static u8 mt352_clock_config [] = { 0x89, 0x38, 0x2d }; static u8 mt352_adc_ctl_1_cfg [] = { 0x8e, 0x40 }; static u8 mt352_acq_ctl [] = { 0x53, 0x50 }; static u8 mt352_ber_config [] = { 0x7c, 0x00, 0x3c }; /* Approx 100 million bits per BER reading */ static struct i2c_init_msg *initmsg; /** * We only write non-default settings, all default settings are * restored by the full mt352_reset sequence. */ mt352_write(mt352_clock_config, sizeof(mt352_clock_config)); udelay(2000); mt352_write(mt352_reset, sizeof(mt352_reset)); mt352_write(mt352_adc_ctl_1_cfg, sizeof(mt352_adc_ctl_1_cfg)); mt352_write(mt352_acq_ctl, sizeof(mt352_acq_ctl)); mt352_write(mt352_ber_config, sizeof(mt352_ber_config)); /** * Write out any extra configuration items for the particular card */ initmsg = card_type->init_routine; while (initmsg->buflen > 0) { mt352_write(initmsg->i2c_buf, initmsg->buflen); if (initmsg->delay_after) udelay(2000); initmsg++; } return 0; } int mt352_sleep(struct dvb_i2c_bus *i2c, struct mt352_card_type *card_type) { static u8 mt352_softdown[] = { 0x89, 0x20, 0x08 }; mt352_write(mt352_softdown, sizeof(mt352_softdown)); return 0; } int mt352_set_parameters (struct dvb_i2c_bus *i2c, struct dvb_frontend_parameters *param, struct mt352_card_type *card_type) { unsigned char buf[14]; unsigned int tps = 0; unsigned char acqctl = (1 << 1) | (1 << 0); /* Force mode, guard */ struct dvb_ofdm_parameters *op = ¶m->u.ofdm; switch (param->inversion) { case INVERSION_ON: acqctl |= (3 << 2); break; case INVERSION_OFF: acqctl |= (2 << 2); break; case INVERSION_AUTO: break; default: return -EINVAL; } switch (op->code_rate_HP) { case FEC_NONE: case FEC_1_2: break; case FEC_2_3: tps = (1 << 7); break; case FEC_3_4: tps = (2 << 7); break; case FEC_5_6: tps = (3 << 7); break; case FEC_7_8: tps = (4 << 7); break; case FEC_AUTO: acqctl |= (5 << 4); /* all parameters auto */ break; default: return -EINVAL; } switch (op->code_rate_LP) { case FEC_NONE: case FEC_1_2: break; case FEC_2_3: tps |= (1 << 4); break; case FEC_3_4: tps |= (2 << 4); break; case FEC_5_6: tps |= (3 << 4); break; case FEC_7_8: tps |= (4 << 4); break; case FEC_AUTO: acqctl |= (5 << 4); /* all parameters auto */ break; default: return -EINVAL; } switch (op->constellation) { case QPSK: break; case QAM_16: tps |= (1 << 13); break; case QAM_64: tps |= (2 << 13); break; case QAM_AUTO: acqctl |= (5 << 4); /* all parameters auto */ break; default: return -EINVAL; } switch (op->transmission_mode) { case TRANSMISSION_MODE_2K: break; case TRANSMISSION_MODE_8K: tps |= (1 << 0); break; case TRANSMISSION_MODE_AUTO: acqctl &= ~(1 << 0); /* unforce mode */ break; default: return -EINVAL; } switch (op->guard_interval) { case GUARD_INTERVAL_1_32: break; case GUARD_INTERVAL_1_16: tps |= (1 << 2); break; case GUARD_INTERVAL_1_8: tps |= (2 << 2); break; case GUARD_INTERVAL_1_4: tps |= (3 << 2); break; case GUARD_INTERVAL_AUTO: acqctl &= ~(1 << 1); /* unforce guard */ break; default: return -EINVAL; } switch (op->hierarchy_information) { case HIERARCHY_NONE: break; case HIERARCHY_1: tps |= (1 << 10); break; case HIERARCHY_2: tps |= (2 << 10); break; case HIERARCHY_4: tps |= (3 << 10); break; case HIERARCHY_AUTO: acqctl |= (5 << 4); /* all parameters auto */ break; default: return -EINVAL; } buf[0] = 0x51; /* TPS_GIVEN_1 and following registers */ buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */ buf[2] = lsb(tps); buf[3] = acqctl; /* ACQ_CTL */ if (op->bandwidth == BANDWIDTH_8_MHZ) { buf[4] = card_type->mt352_trl_nominal_8mhz[0]; buf[5] = card_type->mt352_trl_nominal_8mhz[1]; } else if (op->bandwidth == BANDWIDTH_7_MHZ) { buf[4] = card_type->mt352_trl_nominal_7mhz[0]; buf[5] = card_type->mt352_trl_nominal_7mhz[1]; } else { /* 6MHz */ buf[4] = card_type->mt352_trl_nominal_6mhz[0]; buf[5] = card_type->mt352_trl_nominal_6mhz[1]; } buf[6] = card_type->mt352_input_freq[0]; buf[7] = card_type->mt352_input_freq[1]; buf[8] = card_type->tuner_i2c_addr; /* Calculate frequency and tuner control bytes */ card_type->freq_to_tuner(param->frequency, &buf[9], 0); buf[13] = 0x01; /* TUNER_GO!! */ mt352_write(buf, sizeof(buf)); return 0; } static u8 mt352_read_register (struct dvb_i2c_bus *i2c, struct mt352_card_type *card_type, u8 reg) { int ret; u8 b0 [] = { reg }; u8 b1 [] = { 0 }; struct i2c_msg msg [] = { { .addr = card_type->mt352_i2c_addr, .flags = 0, .buf = b0, .len = 1 }, { .addr = card_type->mt352_i2c_addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } }; ret = i2c->xfer (i2c, msg, 2); if (ret != 2) printk(KERN_WARNING "%s: readreg error (ret == %i)\n", __FUNCTION__, ret); return b1[0]; } static u32 mt352_read_eeprom_dword(struct dvb_i2c_bus *i2c, u8 i2c_addr, u8 base) { u8 id[4]; struct i2c_msg msg[2] = { { .addr = i2c_addr, .flags = 0, .buf = &base, .len = 1 }, { .addr = i2c_addr, .flags = I2C_M_RD, .len = 1, .buf = id } }; int i; for (i = 0; i < 4; i++) { if (i2c->xfer(i2c, msg, 2) != 2) return 0; base++; msg[1].buf++; } return *((u32 *) id); } static struct mt352_card_type *mt352_detect_card_type(struct dvb_i2c_bus *i2c) { int i; for (i = 0; i < NCARDS - 1; i++) if (mt352_read_eeprom_dword(i2c, cardlist[i].eeprom_i2c_addr, cardlist[i].eeprom_pciid_base) == *((u32 *) cardlist[i].pciid)) break; /* Allocate a frontend info template and copy over information from * the cardlist if needed */ if (cardlist[i].fe_info == NULL) { cardlist[i].fe_info = kmalloc(sizeof(struct dvb_frontend_info), GFP_KERNEL); if (! cardlist[i].fe_info) return NULL; memcpy(cardlist[i].fe_info, &mt352_info_template, sizeof(mt352_info_template)); strlcpy(cardlist[i].fe_info->name, cardlist[i].name, sizeof(cardlist[i].fe_info->name)); cardlist[i].fe_info->frequency_stepsize = cardlist[i].frequency_stepsize; } return &cardlist[i]; } int mt352_get_parameters (struct dvb_i2c_bus *i2c, struct dvb_frontend_parameters *param, struct mt352_card_type *card_type) { u16 tps; u8 trl[2]; u8 tuner_regs[4]; struct dvb_ofdm_parameters *op = ¶m->u.ofdm; static const u8 tps_fec_to_api[8] = { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, FEC_AUTO, FEC_AUTO, FEC_AUTO }; if ((mt352_read_register(i2c, card_type, 0x00) & 0xC0) != 0xC0) return -EINVAL; /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because * the mt352 sometimes works with the wrong parameters */ tps = (mt352_read_register(i2c, card_type, 0x1E) << 8) | mt352_read_register(i2c, card_type, 0x1F); trl[0] = mt352_read_register(i2c, card_type, 0x54); trl[1] = mt352_read_register(i2c, card_type, 0x55); op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7]; op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7]; switch ((tps >> 13) & 3) { case 0: op->constellation = QPSK; break; case 1: op->constellation = QAM_16; break; case 2: op->constellation = QAM_64; break; default: op->constellation = QAM_AUTO; break; } op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K; switch ((tps >> 2) & 3) { case 0: op->guard_interval = GUARD_INTERVAL_1_32; break; case 1: op->guard_interval = GUARD_INTERVAL_1_16; break; case 2: op->guard_interval = GUARD_INTERVAL_1_8; break; case 3: op->guard_interval = GUARD_INTERVAL_1_4; break; default: op->guard_interval = GUARD_INTERVAL_AUTO; break; } switch ((tps >> 10) & 7) { case 0: op->hierarchy_information = HIERARCHY_NONE; break; case 1: op->hierarchy_information = HIERARCHY_1; break; case 2: op->hierarchy_information = HIERARCHY_2; break; case 3: op->hierarchy_information = HIERARCHY_4; break; default: op->hierarchy_information = HIERARCHY_AUTO; break; } if (trl[0] == card_type->mt352_trl_nominal_8mhz[0] && trl[1] == card_type->mt352_trl_nominal_8mhz[1]) { op->bandwidth = BANDWIDTH_8_MHZ; } else if (trl[0] == card_type->mt352_trl_nominal_7mhz[0] && trl[1] == card_type->mt352_trl_nominal_7mhz[1]) { op->bandwidth = BANDWIDTH_7_MHZ; } else { op->bandwidth = BANDWIDTH_6_MHZ; } param->inversion = INVERSION_OFF; /* Read the tuner frequency */ tuner_regs[0] = mt352_read_register(i2c, card_type, 0x59); tuner_regs[1] = mt352_read_register(i2c, card_type, 0x5a); tuner_regs[2] = mt352_read_register(i2c, card_type, 0x5b); tuner_regs[3] = mt352_read_register(i2c, card_type, 0x5c); param->frequency = card_type->tuner_to_freq(tuner_regs, 0); /* Adjust the tuner frequency to return the true received frequency */ { u32 freq_offset = (mt352_read_register(i2c, card_type, 0x17) << 16) | (mt352_read_register(i2c, card_type, 0x18) << 8) | mt352_read_register(i2c, card_type, 0x19); int was_negative = 0; int shiftleftcount = 0; if (freq_offset & 0x800000) { freq_offset |= 0xFF000000; freq_offset = - (s32) freq_offset; was_negative = 1; } freq_offset *= 250; /* 64000 / 256 */ while (freq_offset && (freq_offset & 0x80000000) == 0) { shiftleftcount++; freq_offset <<= 1; } freq_offset /= 64; /* 16384 / 256 */ while (freq_offset && (freq_offset & 0x80000000) == 0) { shiftleftcount++; freq_offset <<= 1; } if (op->bandwidth == BANDWIDTH_8_MHZ) freq_offset /= 7; else if (op->bandwidth == BANDWIDTH_6_MHZ) { freq_offset /= 7; freq_offset *= 6; freq_offset /= 8; } else freq_offset /= 8; while (freq_offset && (freq_offset & 0x80000000) == 0) { shiftleftcount++; freq_offset <<= 1; } freq_offset /= 256; freq_offset *= 125; if (op->transmission_mode == TRANSMISSION_MODE_8K) freq_offset /= 4; freq_offset >>= shiftleftcount; if (was_negative) freq_offset = -freq_offset; printk(KERN_DEBUG "Freq: %d, offset: %d, real: %d\n", param->frequency, (s32) freq_offset, param->frequency - (s32) freq_offset); param->frequency -= (s32) freq_offset; } return 0; } static int mt352_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg) { struct dvb_i2c_bus *i2c = fe->i2c; struct mt352_card_type *card_type = fe->data; u8 r,snr; fe_status_t *status; u16 signal; #ifdef FE_GET_TUNE_SETTINGS struct dvb_frontend_tune_settings *fe_tune_settings; #endif switch (cmd) { case FE_GET_INFO: memcpy(arg, card_type->fe_info, sizeof(struct dvb_frontend_info)); break; case FE_READ_STATUS: status = arg; *status = 0; r = mt352_read_register(i2c, card_type, 0x00); if (r & (1 << 4)) *status = FE_HAS_CARRIER; if (r & (1 << 1)) *status |= FE_HAS_VITERBI; if (r & (1 << 5)) *status |= FE_HAS_LOCK; r = mt352_read_register(i2c, card_type, 0x01); if (r & (1 << 1)) *status |= FE_HAS_SYNC; r = mt352_read_register(i2c, card_type, 0x03); if (r & (1 << 6)) *status |= FE_HAS_SIGNAL; break; case FE_READ_BER: *((u32 *) arg) = (mt352_read_register(i2c, card_type, 0x0D) << 16) | (mt352_read_register(i2c, card_type, 0x0E) << 8) | (mt352_read_register(i2c, card_type, 0x0F)); break; case FE_READ_SIGNAL_STRENGTH: signal = ((mt352_read_register(i2c, card_type, 0x14) & 0x0f) << 8) | (mt352_read_register(i2c, card_type, 0x15)); *((u16*) arg) = ~signal; break; case FE_READ_SNR: snr = mt352_read_register(i2c, card_type, 0x09); *((u16*) arg) = (snr << 8) | snr; break; case FE_READ_UNCORRECTED_BLOCKS: *(u32*) arg = (mt352_read_register(i2c, card_type, 0x10) << 8) | (mt352_read_register(i2c, card_type, 0x11)); break; case FE_SET_FRONTEND: return mt352_set_parameters (i2c, (struct dvb_frontend_parameters *) arg, card_type); case FE_GET_FRONTEND: return mt352_get_parameters (i2c, (struct dvb_frontend_parameters *) arg, card_type); #ifdef FE_GET_TUNE_SETTINGS case FE_GET_TUNE_SETTINGS: fe_tune_settings = (struct dvb_frontend_tune_settings *) arg; fe_tune_settings->min_delay_ms = 800; fe_tune_settings->step_size = 0; /* No need to step with the MT352 demodulator, */ fe_tune_settings->max_drift = 0; /* it has a good capture range. */ break; #endif case FE_SLEEP: return mt352_sleep(i2c, card_type); case FE_INIT: return mt352_init(i2c, card_type); default: return -EOPNOTSUPP; } return 0; } static int mt352_attach (struct dvb_i2c_bus *i2c, void **data) { struct mt352_card_type *card_type; static u8 mt352_reset_attach [] = { 0x50, 0xC0 }; /* Detect our card type from any attached EEPROM */ *data = card_type = mt352_detect_card_type(i2c); if (card_type == NULL) return -ENOMEM; /* Probe to make sure the mt352 responds */ if (mt352_read_register(i2c, card_type, 0x7f) == 0x13) { /* Do a "hard" reset */ mt352_write(mt352_reset_attach,sizeof(mt352_reset_attach)); /* Don't waste power and (maybe) pci bandwidth */ mt352_sleep(i2c, card_type); return dvb_register_frontend(mt352_ioctl, i2c, (void *) card_type, card_type->fe_info); } return -ENODEV; } static void mt352_detach (struct dvb_i2c_bus *i2c, void *data) { struct mt352_card_type *card_type = data; mt352_sleep(i2c, card_type); dvb_unregister_frontend(mt352_ioctl, i2c); } static int __init init_mt352 (void) { return dvb_register_i2c_device(NULL, mt352_attach, mt352_detach); } static void __exit exit_mt352 (void) { int i; dvb_unregister_i2c_device(mt352_attach); /* Unallocate any frontend information structures */ for (i = 0; i < NCARDS; i++) if (cardlist[i].fe_info != NULL) kfree(cardlist[i].fe_info); } module_init(init_mt352); module_exit(exit_mt352); MODULE_DESCRIPTION("DVB-T MT352 Zarlink"); MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Chris Pascoe"); MODULE_LICENSE("GPL");