This page was last edited on Monday, 28 August 2006 12:25 PM
Objective of the Project
The purpose of this project is:
- to introduce Mentor Graphics Development Tools.
- to research for the latest VLSI technology.
Overview of the Project
You will work either individually or in groups of TWO people. Group of two is recommended as there will be no difference in the marking scheme.
- The first part of the project (5 marks) involves research into the latest
development of VLSI technology and presenting your group findings to the
rest of the class.
- The second part of the project (15 marks) involves the building of a Boolean function on VLSI using Mentor Graphics software.
Completion of self learning Mentor Graphics tutorials are highly recommended before starting the second part of the assignment. They contain the necessary steps and hints to make the second part of this project a relatively easy task.
Part 1 (5 marks) "Electronic News"
Presentation time: 18th September at 4:30pm.
Find the latest development in the field of VLSI design, and prepare a presentation of no more than 5 minutes per group. The group will present in front of the class during the tutorial/prac session timeslot. You will have access to a laptop (with Microsoft office & Acrobat reader installed) connected to a projector during the presentation.
Make sure you find the latest development relevant to VLSI field to present.
Keep the class interested. Make your presentation interesting. We all want to learn something new everyday.
The most popular and interesting presentation will get a very good mark in this part!
Please bring your presentation file via CD-Rom as it is probably the safest medium. Use USB drive or floppy at your own risk.
Some suggestions for the topics are:
- Latest fabrication technology and its performance.
- Latest processors (PC, RISC, Digital Signal Processors etc) and its performance.
- Latest FPGA offerings and their architectural features.
- Newest toolset in design creations and its ease of use.
- Toolset in design verifications.
- New architecture for computations.
- Newest low-k materials for fabrication.
- Analogue circuit synthesis.
- New design paradigms.
- MicroElectronicMechanical Systems.
Part 2 (15 marks) "VLSI Design"
Assessment Time: 2nd October from 3:30pm onwards. Report due on 29th September, 5pm.
In this part, you will first implement a logic function as a complex CMOS gate.
When you are ready to start this part, please email Simon the names of the members of your group. You will be given a group number and then please GET YOUR BOOLEAN FUNCTION HERE. Note that if you work by yourself, the same criteria of assessment is applied to you as well as for groups.
Schematics
Develop the schematic for your CMOS complex gate, and then verify the functionality of your schematic.
The input signals are ONLY available as active high inputs. The output is a capacitive load of 1pF. Keep the default nmos & pmos size for now.
Rise Time, Fall Time and Delay measurement
Identify the combination of inputs which will give you the worst-case scenario for the rise time of your gate. Take a record of these inputs and time.
Similarly identify the combination of inputs which will give you the worst-case scenario for the fall time of your gate. Take a record of these inputs and time.
Using the inputs above, or otherwise, measure the worst-case scenario for the delay of your gate.
Noise margins
Using any ONE set of input, investigate the noise margins for that particular logic input of your gate. A quick discussion about noise margin is given in section 5.3 of Rabaey.
Transistor Sizing
Adjust the sizing of the transistors such that the rise time and the fall time of your gate is AT LEAST halved. How does this affect the delay time? Aim to halve the delay time too if possible.
Layout
Develop the layout of your complex gate, in the form of full custom cell layout based on the sizing you've obtained above.
Perform layout verification so that your layout matches your schematic exactly.
Dynamic Logic or Transmission Gate
Now implement your function using Dynamic Logic (or Domino Logic) or Transmission Gate Logic and develop its layout. It will be driving the same output load as the CMOS complex gate. Investigate the rise time, fall time, delay and the noise margin of this design method.
Post-layout work
Carry out post-layout simulations of the two layouts. Compare the difference in the electrical properties, area and performance of the designs.
Report
You are asked to document the process of deriving the timing information and noise margin of your design. Include any graphs, schematics, simulations, plots as you see fit. This report is NOT about length and word - but to reflect on the process from your first schematics (with default ratio), your ideas and design decisions, and the results based on those changes.
Criteria of assessment
Part 1:
| Criterion / Grade | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Length | too long / too short | appropriate length for the material; adhere to the 5 min guideline | |||||
| Clarity | audience unable to understand | audience only understand parts of the concepts/material | audience can fully understand the concepts and material presented | ||||
| "Interesting" | Not interesting at all | acceptable | Interesting | Pretty interesting | Very interesting | Engage the audience at all times | |
| Recent development | old development | Recent | Latest, state of the art | ||||
| Content and range | Totally irrelevant to VLSI technology | Some links to VLSI technology; Material is too broad/narrow | Totally relevant to VLSI technology; Included the correct amount of material | ||||
| Critical Review | No understanding of the presented material | Acceptable amount of review is carried out before presentation | Showed that some judgement has been applied, some selection of material. | Applied critical thinking and review in the selection, presentation and creating of the presentation | |||
So, if you want to obtain a high mark:
- Presentation: a maximum of 5 minute per group during tutorial session.
- The more interesting the presentation, the higher the grade you receive.
- The newer the development shown in the presentation, the higher the grade you receive.
- The presentation must be linked to the VLSI technology, for example, fabrication, deep sub-micron, latest tools, architecture, new materials, new methodology etc.
- The class will vote for the best presentation, in which the group will receive a very good mark and a prize.
Part 2 (Draft):
| Criterion / Grade | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Proficiency of MGC tools | Cannot use MGC tools | Limited ability | Acceptable level of skills, refer to instructions often | Good knowledge of the tools to complete the project | Very proficient with MGC tools, and showed evidence of investigation to use the tools more effectively | ||
| Explanation, understanding of the circuit | No understanding of the circuit | Limited understanding | Can relate some parts of the layout with the schematics | Can show the equivalence between layout and circuit | Understand the entire design procedure and the reasons behind | Show complete understanding of procedure. Take advantage of the design process to optimise the circuit, layout with the help of the MGC tools. | |
| Method of obtaining timing information | No idea | Major flaws | Correct, with minor mistakes | Correct, with supporting evidence, experiments and record of results. | |||
| Optimised layout | Incomplete; Layout not optimised | Half completed; Optimised "by accident" | Almost Complete, with minor errors; Attempt in optimisation is acceptable | Complete, with no errors; Justified the reason behind optimisation, identify any trade-off. | |||
| Layout using dynamic logic or transmission gates | Incomplete | Almost Complete, with minor errors | Complete | ||||
| Connectivity, design rules | Fail all tests | Passed one test only | Passed most tests | Passed all tests | |||
| Delay, electrical properties | No extraction or calculation | Obtained properties but does not use properly | Showed understanding and use properties to explain performance, optimisation, etc | Demonstrate how the properties can be controlled and improved, and showed some design cycles | |||
| Report | Too long/short, illegible, no relevance | Correct length, appropriate format, relevance to the calculation and design process, helpful to understand the design | "A pleasure to read!" | ||||
Assessment day criteria sheet (pdf version).
In short, if you want a good mark for this part:
- Proficiency in using the Mentor Graphics Toolset - the assessment will be carried out interactively with the lecturer/tutor, as well as a hand-in report per group of no more than 4 pages.
- Able to explain the functions of various parts of the circuit and the layout.
- Able to carry out tasks as instructed by the lecturer/tutor during assessment (these tasks will be very similar to the work you have carried out in the tutorial).
- Optimised mask layout of the completed cell (the complex gate) in electronic form.
- The cell should be as compact as possible while satisfying the constraints. It usually means using a minimum number of transistors and/or a minimum silicon area.
- Connectivity is maintained within Mentor Graphics.
- All design rules are adhered to with the appropriate reports from IC Rules as proofs.
- Electrical properties are extracted from layout.
- Any missing electrical properties are located and the parameters of the custom design are obtained using Mentor Graphics Tools.
Last update: Monday, 28. August 2006 12:24