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 Architectural Mapping for Coarse-Grained Heterogeneous Reconfigurable System on Chip
Seminar Information

Speaker: Ian Clough

When: 3:00PM Tuesday 30th August 2005

Venue: 78-622

Abstract:

As an emerging technology, Digital Radio (or Software Defined Radio) shows promise in terms of improved audio quality, enhanced content delivery and multifunctional platforms. However, there are a number of different standards for Digital Radio, which can vary from country to country and region to region. As a consequence, there is a desire to make Software Defined Radio, where the Radio receiver can automatically choose the most suitable (or available) mode of reception and method of content delivery. The high data rates of Digital Radio require very high processing capabilities, and these may not always be best achieved in software. Thus there will be a need to implement some processing in hardware. However, whatever platform is chosen, an Operating System will be required to manage the system resources, especially battery life, through improved efficiency.

This dynamic environment may be harder to control than one which is "ready for anything", but it can also be more efficient, through design, and therefore more suited to the portable environment where size, weight and battery life are important factors. It would be reasonable to consider this environment as a heterogeneous system, consisting of different devices, processing elements, interfaces, users, states etc. A Heterogeneous Reconfigurable System on Chip (HRSoC), which has a controlling CPU attached to a reconfigurable fabric or array, allows us to design a Digital Radio receiver in incremental stages which can have dynamic implementation of various functions according to processing need and power restrictions, such as loading an audio decoder module when needed, or switching off a video decoder if no video information (or display) is present. It is also possible to compare the implementation of these tasks in software as well as hardware, and to determine how to optimise the use of available HRSoC resources.

I will be investigating the role of the controlling CPU, the Real-Time Operating System (RTOS), the energy, area and control complexity of the reconfigurable array, and how to map the Digital Radio algorithm onto both hardware and software.

Biography:

Ian Clough is a PhD student in Embedded Systems Research Division, working on Software Defined Radio as part of a DEST-funded International Science Linkages project with the European Union Framework 6 research project entitled "Smart Chips for Smart Surroundings".

Contact: Professor Neil Bergmann