Speaker: Venkatesh Vasudevan
When: 2:00PM Tuesday 22nd August 2006
Venue: General Purpose South 78-622
Abstract:
Safety Critical Systems have been implemented for a long time using traditional semiconductor devices such as microprocessors, microcontrollers and other ASICS (Application Specific Integrated Circuits). Use of FPGA’s has commenced recently with just a few institutions implementing practical solutions on them. Little work has been done in making software reliable on FPGA’s viz improving software reliability in the event of SEU’s (Single Event Upsets) caused by neutron bombardment or incident cosmic rays or alpha particle collision.
This paper presents an implementation that improves the reliability of software running on the FPGA in the event of various hardware failures like SEU’s, bitstream faults and configuration faults due to faulty PROM’s / flash. The concept used is a well known one but implemented in a new technology. The code conforms to a particular safety critical coding standard which is popular in industry.
Biography:
The author is currently pursuing PhD under Prof Neil Bergmann in the area of FPGA based architectures for safety critical systems. He was previously employed as Senior Design Engineer in semiconductor major Conexant Systems Inc (California based) where he worked on the latest craze in broadband communications in the U.S, Gigabit capable passive optical networks (GPON). Prior to that he was employed as Hardware Design Engineer in Siemens Information Systems Ltd. The author holds a M.E degree in VLSI System Design from Griffith University, QLD, Australia.
Contact: Professor Neil Bergmann