diff -aurN ml401_emb_ref/system.mhs ml401_uclinux_ref/system.mhs
--- ml401_emb_ref/system.mhs	2004-11-25 04:15:08.000000000 +1000
+++ ml401_uclinux_ref/system.mhs	2005-02-19 21:24:44.000000000 +1000
@@ -218,21 +218,52 @@
 
 BEGIN microblaze
  PARAMETER INSTANCE = microblaze_0
- PARAMETER HW_VER = 2.10.a
+ PARAMETER HW_VER = 3.00.a
+ PARAMETER C_USE_BARREL = 1
+ PARAMETER C_USE_DIV = 0
+ PARAMETER C_USE_MSR_INSTR = 1
  PARAMETER C_DEBUG_ENABLED = 1
+ PARAMETER C_NUMBER_OF_PC_BRK = 2
+ PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
+ PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
+ PARAMETER C_USE_ICACHE = 1
+ PARAMETER C_ICACHE_BASEADDR = 0x10000000
+ PARAMETER C_ICACHE_HIGHADDR = 0x13FFFFFF
+ PARAMETER C_CACHE_BYTE_SIZE = 16384
+ PARAMETER C_ADDR_TAG_BITS = 11
+ PARAMETER C_USE_DCACHE = 1
+ PARAMETER C_DCACHE_BASEADDR = 0x10000000
+ PARAMETER C_DCACHE_HIGHADDR = 0x13FFFFFF
+ PARAMETER C_DCACHE_BYTE_SIZE = 16384
+ PARAMETER C_DCACHE_ADDR_TAG = 11
+ PARAMETER C_FSL_LINKS = 1
+ BUS_INTERFACE SFSL0 = download_link
  BUS_INTERFACE DLMB = lmb_v10_1
  BUS_INTERFACE ILMB = lmb_v10_0
  BUS_INTERFACE DOPB = opb_v20_0
  BUS_INTERFACE IOPB = opb_v20_0
  PORT CLK = opb_clk
  PORT Interrupt = ext_irq
+ # Support for OPB_IBA chipscope core
+ # stop MB when ChipScope triggers
+ # PORT DBG_STOP = mb_stop
+ # Trigger Chipscope if MB is halted (by xmd/gdb etc)
+ # PORT MB_Halted = mb_halt_trig
+END
+
+BEGIN fsl_v20
+ PARAMETER INSTANCE = download_link
+ PARAMETER HW_VER = 2.00.a
+ PARAMETER C_EXT_RESET_HIGH = 0
+ PORT SYS_Rst = sys_rst
+ PORT FSL_Clk = opb_clk
 END
 
 BEGIN lmb_bram_if_cntlr
  PARAMETER INSTANCE = lmb_bram_if_cntlr_0
  PARAMETER HW_VER = 1.00.b
- PARAMETER C_BASEADDR = 0x0000_0000
- PARAMETER C_HIGHADDR = 0x0000_ffff
+ PARAMETER C_BASEADDR = 0x00000000
+ PARAMETER C_HIGHADDR = 0x0000ffff
  BUS_INTERFACE SLMB = lmb_v10_1
  BUS_INTERFACE BRAM_PORT = conn_0
 END
@@ -247,8 +278,8 @@
 BEGIN lmb_bram_if_cntlr
  PARAMETER INSTANCE = lmb_bram_if_cntlr_1
  PARAMETER HW_VER = 1.00.b
- PARAMETER C_BASEADDR = 0x0000_0000
- PARAMETER C_HIGHADDR = 0x0000_ffff
+ PARAMETER C_BASEADDR = 0x00000000
+ PARAMETER C_HIGHADDR = 0x0000ffff
  BUS_INTERFACE SLMB = lmb_v10_0
  BUS_INTERFACE BRAM_PORT = conn_1
 END
@@ -290,7 +321,9 @@
  PARAMETER C_MB_DBG_PORTS = 1
  PARAMETER C_USE_UART = 1
  PARAMETER C_UART_WIDTH = 8
+ PARAMETER C_WRITE_FSL_PORTS = 1
  BUS_INTERFACE SOPB = opb_v20_0
+ BUS_INTERFACE MFSL0 = download_link
  PORT Interrupt = mdm_intr
 END
 
@@ -301,7 +334,7 @@
  PARAMETER C_HIGHADDR = 0xD1000FDF
  BUS_INTERFACE SOPB = opb_v20_0
  PORT OPB_Clk = opb_clk
- PORT Intr = mdm_intr & uart_intr & ps2_1_intr & ps2_2_intr & iic_intr & ac97_play_intr & ac97_record_intr & sysace_intr & phy_mii_int & timer_intr & usb_hpi_int
+ PORT Intr = mdm_intr & uart_intr & ps2_1_intr & ps2_2_intr & iic_intr & ac97_play_intr & ac97_record_intr & sysace_intr & phy_mii_int & ethernet_intr & usb_hpi_int & timer_intr
  PORT Irq = ext_irq
 END
 
@@ -317,20 +350,36 @@
  PORT Interrupt = timer_intr
 END
 
-BEGIN opb_uart16550
- PARAMETER INSTANCE = opb_uart16550_0
- PARAMETER HW_VER = 1.00.c
- PARAMETER C_IS_A_16550 = 1
+#BEGIN opb_uart16550
+# PARAMETER INSTANCE = opb_uart16550_0
+# PARAMETER HW_VER = 1.00.c
+# PARAMETER C_IS_A_16550 = 1
+# PARAMETER C_BASEADDR = 0xa0000000
+# PARAMETER C_HIGHADDR = 0xa0001FFF
+# BUS_INTERFACE SOPB = opb_v20_0
+# PORT dsrN = net_vcc
+# PORT riN = net_vcc
+# PORT dcdN = net_vcc
+# PORT ctsN = net_gnd
+# PORT sin = uart_RX
+# PORT sout = uart_TX
+# PORT IP2INTC_Irpt = uart_intr
+#END
+BEGIN opb_uartlite
+ PARAMETER INSTANCE = console_uart
+ PARAMETER HW_VER = 1.00.b
+ PARAMETER C_BAUDRATE = 115200
+ PARAMETER C_DATA_BITS = 8
+ PARAMETER C_USE_PARITY = 0
+ PARAMETER C_ODD_PARITY = 0
+ PARAMETER C_CLK_FREQ = 100_000_000
  PARAMETER C_BASEADDR = 0xa0000000
- PARAMETER C_HIGHADDR = 0xa0001FFF
+ PARAMETER C_HIGHADDR = 0xa0001fff
  BUS_INTERFACE SOPB = opb_v20_0
- PORT dsrN = net_vcc
- PORT riN = net_vcc
- PORT dcdN = net_vcc
- PORT ctsN = net_gnd
- PORT sin = uart_RX
- PORT sout = uart_TX
- PORT IP2INTC_Irpt = uart_intr
+ PORT Interrupt = uart_intr
+ PORT OPB_Clk = opb_clk
+ PORT RX = uart_RX
+ PORT TX = uart_TX
 END
 
 BEGIN opb_gpio
@@ -412,8 +461,8 @@
  PARAMETER HW_VER = 1.02.a
 # PARAMETER C_DCR_INTFCE = 0
  BUS_INTERFACE SDCR = dcr_v29_0
- PARAMETER C_BASEADDR = 0b0000010000
- PARAMETER C_HIGHADDR = 0b0000011111
+ PARAMETER C_BASEADDR = 0x10
+ PARAMETER C_HIGHADDR = 0x1F
  PARAMETER C_NUM_OPBCLK_PLB2OPB_REARB = 100
  PORT Bus_Error_Det = plb_error_det
  PORT PLB_Clk = plb_clk
@@ -472,8 +521,8 @@
  PARAMETER C_RNG1_PREFETCH = 0
  PARAMETER C_RNG1_LINE = 1
 # PARAMETER C_OPB_BASEADDR = 0x00000000
- PARAMETER C_DCR_BASEADDR = 0b0000001000
- PARAMETER C_DCR_HIGHADDR = 0b0000001011
+ PARAMETER C_DCR_BASEADDR = 0x8
+ PARAMETER C_DCR_HIGHADDR = 0xF
  BUS_INTERFACE SOPB = opb_v20_0
  BUS_INTERFACE MPLB = plb_v34_0
 # swap the next two lines if plb2opb bridge is used
diff -aurN ml401_emb_ref/system.mss ml401_uclinux_ref/system.mss
--- ml401_emb_ref/system.mss	2004-11-25 04:15:08.000000000 +1000
+++ ml401_uclinux_ref/system.mss	2005-02-19 22:05:07.000000000 +1000
@@ -1,31 +1,37 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#     
-#     (c) Copyright 2004 Xilinx, Inc.
-#     All rights reserved.
-#
 
+# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION  AS IS 
+# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
+# XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
+# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
+# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
+# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
+# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
+# FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
+# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE.
+# (c) Copyright 2004 Xilinx, Inc.
+# All rights reserved.
  PARAMETER VERSION = 2.2.0
 
 
 BEGIN OS
- PARAMETER OS_NAME = standalone
+ PARAMETER OS_NAME = uclinux
  PARAMETER OS_VER = 1.00.a
  PARAMETER PROC_INSTANCE = microblaze_0
- PARAMETER stdin = opb_uart16550_0
- PARAMETER stdout = opb_uart16550_0
+ PARAMETER stdin = console_uart
+ PARAMETER stdout = console_uart
+ PARAMETER main_memory = plb_ddr_0
+ PARAMETER main_memory_bank = 0
+# over-ride main memory size to 64MB (vs 256MB with mirroring)
+ PARAMETER main_memory_size = 0x00400000
+ PARAMETER flash_memory = opb_emc_0
+ PARAMETER flash_memory_bank = 1
+ PARAMETER lmb_memory = lmb_bram_if_cntlr_0
+# where to copy autoconfig.in file
+ PARAMETER target_dir = /mnt/home2/jwilliam/cvstest/uClinux-dist/linux-2.4.x/arch/microblaze/platform/uclinux-auto
 END
 
 
@@ -35,6 +41,7 @@
  PARAMETER HW_INSTANCE = microblaze_0
  PARAMETER COMPILER = mb-gcc
  PARAMETER ARCHIVER = mb-ar
+ PARAMETER CORE_CLOCK_FREQ_HZ = 100000000
 END
 
 
@@ -66,15 +73,12 @@
  PARAMETER DRIVER_NAME = tmrctr
  PARAMETER DRIVER_VER = 1.00.b
  PARAMETER HW_INSTANCE = opb_timer_0
- PARAMETER LEVEL = 0
 END
 
 BEGIN DRIVER
- PARAMETER HW_INSTANCE = opb_uart16550_0
- PARAMETER DRIVER_NAME = uartns550
+ PARAMETER HW_INSTANCE = console_uart
+ PARAMETER DRIVER_NAME = uartlite
  PARAMETER DRIVER_VER = 1.00.b
- PARAMETER LEVEL = 0
- PARAMETER CLOCK_HZ = 100000000
 END
 
 BEGIN DRIVER
@@ -87,14 +91,12 @@
  PARAMETER HW_INSTANCE = opb_ps2_dual_ref_0
  PARAMETER DRIVER_NAME = ps2_ref
  PARAMETER DRIVER_VER = 1.00.a
- PARAMETER LEVEL = 1
 END
 
 BEGIN DRIVER
  PARAMETER HW_INSTANCE = opb_iic_0
  PARAMETER DRIVER_NAME = iic
  PARAMETER DRIVER_VER = 1.01.d
- PARAMETER LEVEL = 0
 END
 
 BEGIN DRIVER
@@ -107,14 +109,12 @@
  PARAMETER HW_INSTANCE = opb_sysace_0
  PARAMETER DRIVER_NAME = sysace
  PARAMETER DRIVER_VER = 1.00.a
- PARAMETER LEVEL = 1
 END
 
 BEGIN DRIVER
  PARAMETER HW_INSTANCE = plb_tft_cntlr_ref_0
  PARAMETER DRIVER_NAME = tft_ref
  PARAMETER DRIVER_VER = 1.00.a
- PARAMETER LEVEL = 1
 END
 
 BEGIN DRIVER
diff -aurN ml401_emb_ref/system.xmp ml401_uclinux_ref/system.xmp
--- ml401_emb_ref/system.xmp	2004-11-25 04:15:08.000000000 +1000
+++ ml401_uclinux_ref/system.xmp	2005-02-19 22:05:48.000000000 +1000
@@ -1,21 +1,3 @@
-#
-#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
-#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-#     FOR A PARTICULAR PURPOSE.
-#     
-#     (c) Copyright 2004 Xilinx, Inc.
-#     All rights reserved.
-#
 #Please do not modify this file by hand
 XmpVersion: 6.3
 IntStyle: default