[microblaze-uclinux] Microblaze caches and uClinux

[John Williams <jwilliams@itee.uq.edu.au>]

Hi folks,

An interesting result to report - I received the EDK3.2 release 
yesterday, and have created a new version of the mbvanilla platform with 
instruction and data caches enabled (available soon for download).

The processor and bus are clocked at 100Mhz.  Previously, the delay loop 
calibration in the kernel startup sequence reported around 1.8 BogoMIPS. 
  After adding cache support to the kernel, it now reports ... wait for 
it... a whopping 49.25 bogomips!  That's correct, an increase by a 
factor of 27.

It seems that the microblaze was previously living a tortured life of 
perpetual pipeline stalls when executing from external SRAM.  Be free 
little processor, be free!

I'm not doing anything tricky, just a 64K cache (instruction and data), 
and enabling it early in the kernel boot process.  Of course, with a 
large number of user processes running some of this speedup will be lost 
through cache-thrashing, but tricks like cache-locking the interrupt 
handlers etc may remedy this to some extent.  These and other 
optimisations are in the long term wishlist.

I know that Goran Bilski (the Microblaze designer) and other Xilinx 
people are listening - congratulations on a powerful new addition to 
this cool little processor.

John