Hi John, I have the offical Xilinx Ethernet Core running on the V2MB1000 Board but I experienced the same problem: I could not reach 100 MHz. I was able to modify the webserver for the V2MB1000 and get it running at 67 MHz using a DCM (24MHZ * 14 / 5 = 67.2 MHz). I do not think that this will be a great help but if you want to I can send you the project. On my own design (XC2V2000-5) I have the Ethernetcore and the MB running at 90 MHz. It is possible to reach 100 MHz but only with a lot of PAR effort. If you take a look at the opb_ethernet v1.00k documentation in table 26 you can see that they used a VirtexII with speedgrade -6 to achieve the performance (Take a look at the included table copied from the docu.) I dare to doubt that you will reach 100MHz in a XC2V1000-4 (which is on my insight board, and I guess thats on your board,too.) Therefore I would not spend much time on performance. I would suggest to slow down your MB maybe even downto 50 MHz (be careful, this will allow only 10MBit on the emac) and get the emac working there. Once it runs I do not see a problem to implement it in faster hardware / higher speedgrade. Back to booting from flash: For a hardware guy like me this is a big improvement. Could you provide the code or the bootloader (it may seem trivial to you but not to me ;-). Have you tried execute part of the kernel from flash (leave all read only data in the flash and copy only initialized data to ram, "code relocation")? A few weeks ago I spent some time on linker scripts but since I am the VHDL-guy and my program still fits into the onchip BRAM I stopped working on that. Thanks Jan -----Ursprüngliche Nachricht----- Von: John Williams [mailto:jwilliams@itee.uq.edu.au] Gesendet: Donnerstag, 22. Mai 2003 02:57 An: microblaze-uclinux@itee.uq.edu.au Betreff: [microblaze-uclinux] update Hi everyone, A quick update - my Insight board is now self booting with a uclinux kernel. It's more of a moral rather than technical achievement, but I'm not complaining! I've uploaded a kernel and file system image into the flash (via xmd and Jan's tcl flash scripts), and written trivial a bootloader stored into bram that just copies the image from flash to SRAM, then does the leap to execute the kernel. I wrote the fpga configuration into the little xc18v04 prom on the board, and now when I hit the "prog" button on the, it boots itself! Status of the rest of the port is as follows - I've temporarily broken the file system because I've dropped the blkmem driver (which is on its way to official deprecation in the linux tree), and migrated to the MTD drivers, which support both RAM, ROM and Flash-based memory. This means I'll have a consistent low level memory driver, and it should be trivial to overlay JFFS2 (a wear-levelling journalled flash file system) over the flash. Once I get the file system back up and running then I'll continue to iron out the wrinkles in the rest of the port. I have a request - does anybody have a *working* example using the ethernet MAC peripheral on the Insight XC2V1K board? The webserver example published by Xilinx targets the V2Pro boards, and after modifiying it for the V2 board I simply cannot get it to synthesize for a 100MHz clock - maximum I can attain is about 90Mhz even with maximum PAR effort. We had some interactions with one of the Insight engineers but still couldn't get it to fly. Has anybody actually managed to get this peripheral working on the Insight XC2V1K board? If so, I need your help, even if you can just zip up a project and send it to me. Thanks, John
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