[microblaze-uclinux] microblaze + DDR

[John Williams <jwilliams@itee.uq.edu.au>]

Hi folks,

Has anybody had any luck with the opb_ddr controller and microblaze? 
I'm trying to get this up and running on the insight board and am having 
a pretty hard time of it.

I've downloaded Insight's ddr_test_wrapper bitstream and it works, so 
there's nothing wrong with my board, but for some biazrre reason they 
didn't distribute the design files!

For example, as far as I can tell the insight manual doesn't even 
properly document which FPGA pin is connected to the external DDR clock 
feedback path.  I think it's "F13", but various things I'm seeing 
suggest this may be wrong.

I'm trying to get the clock generation going as per the OPB_DDR 
documentation.  If I route the ddr_clk, ddr_clkn and ddr_fb_clk signals 
to general user io pins (the LVDS bank) and make the clock feedback path 
myself with a jumper wire, it works fine (well, at least both DCMs 
achieve lock).  However, if I route these signals to the pins as 
described in (or inferred from) the Insight manual, I can't get DCM lock 
on the feedback path.

If anybody can help out on this I would be most appreciative - I've more 
  or less hit the limit of what I can do in the 1MB SRAM, so I need to 
get this working.

Thanks,

John

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