Re: [microblaze-uclinux] microblaze + DDR

[John Williams <jwilliams@itee.uq.edu.au>]

Hi everyone,

Well happily I can reply to my own message and say "no worries, it's 
working now".  Full marks to Nasser Poureh from Insight who responded in 
a flash to an email I sent him, he got back to me with a working 
microblaze + ddr example.  I took that stuff across to my ddr test 
hardware and i'm up and running already.

Next is to integrate it into mbvailla which shouldn't take long, then 
the kernel with have a massive 32MB to play with! :)

I'm happy to pass on my ddr example if anybody wants it, otherwise 
you'll just see the changes folded in to the mbvanilla target in the 
next few days.  The main trick (or at least what I was missing) with the 
ddr was specifying the correct IOSTANDARD constraints...   After that 
it's all pretty plain sailing.

Regards,

John


John Williams wrote:
> Hi folks,
> 
> Has anybody had any luck with the opb_ddr controller and microblaze? I'm 
> trying to get this up and running on the insight board and am having a 
> pretty hard time of it.
> 
> I've downloaded Insight's ddr_test_wrapper bitstream and it works, so 
> there's nothing wrong with my board, but for some biazrre reason they 
> didn't distribute the design files!
> 
> For example, as far as I can tell the insight manual doesn't even 
> properly document which FPGA pin is connected to the external DDR clock 
> feedback path.  I think it's "F13", but various things I'm seeing 
> suggest this may be wrong.
> 
> I'm trying to get the clock generation going as per the OPB_DDR 
> documentation.  If I route the ddr_clk, ddr_clkn and ddr_fb_clk signals 
> to general user io pins (the LVDS bank) and make the clock feedback path 
> myself with a jumper wire, it works fine (well, at least both DCMs 
> achieve lock).  However, if I route these signals to the pins as 
> described in (or inferred from) the Insight manual, I can't get DCM lock 
> on the feedback path.
> 
> If anybody can help out on this I would be most appreciative - I've more 
>  or less hit the limit of what I can do in the 1MB SRAM, so I need to 
> get this working.
> 
> Thanks,
> 
> John
> 
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-- 
Dr John Williams, Research Fellow,
Reconfigurable Computing, School of ITEE
University of Queensland, Brisbane, Australia
Ph : (07) 3365 8305

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