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[microblaze-uclinux] ethernet + EMC

To: microblaze-uclinux@itee.uq.edu.au
Subject: [microblaze-uclinux] ethernet + EMC
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Tue, 26 Aug 2003 17:37:35 +1000
Organization: ITEE, University of Queensland
Reply-to: microblaze-uclinux@itee.uq.edu.au
Sender: owner-microblaze-uclinux@itee.uq.edu.au
User-agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030529

Hi folks,

Trying to bring up networking on uClinux, first step I've put a xilinx 
ethernet MAC core in my project (surprisingly enough called 
mbvanilla_net :).

Anyway I've found that when I include the MAC core, all of a sudden my 
EMC peripheral (which drives the flash and SRAM) doesn't work.  The low 
byte of all reads in the EMC address space returns 0xFF...the high 3 
bytes are fine...

I can query the ethernet MAC device ID register, and the BRAM and DDR 
memory are unaffected.

So, I can upload an image direct into DDR and execute it, no problems, 
however my bootloading process of reading from flash and so on can't 
work - all reads from flash are corrupted by this 0xFF byte.

Has anybody had any experiences, positive or negative, re: using the EMC 
and EMAC in the same target?  I've attached the mhs and ucf files for 
reference.

Any ideas of where to look would be greatly appreciated.

Thanks,

John

# Parameters
PARAMETER VERSION = 2.0.0

# Global Ports

PORT ext_clk = ext_clk, DIR = IN
PORT ddr_clk_fb = ddr_clk_fb, DIR = IN

PORT sys_rstn = sys_rstn, DIR = IN

PORT console_uart_rx = console_uart_rx, DIR = IN
PORT console_uart_tx = console_uart_tx, DIR = OUT

PORT debug_uart_rx = debug_uart_rx, DIR = IN
PORT debug_uart_tx = debug_uart_tx, DIR = OUT

PORT sram_cen = sram_cen , DIR = OUT, VEC = [0:1]
PORT sram_addr = sram_addr , DIR = OUT, VEC = [0:31]
PORT sram_ben = sram_ben , DIR = OUT, VEC = [0:3]
PORT sram_data = sram_data , DIR = INOUT, VEC = [0:31]
PORT sram_oen = sram_oen, DIR = OUT
PORT sram_wen = sram_wen, DIR = OUT
PORT sram_rst = sram_rst, DIR = OUT

PORT gpio = gpio, DIR = INOUT, VEC = [0:31]

PORT ddr_clk = ddr_clk, DIR = OUT
PORT ddr_clkn = ddr_clkn, DIR = OUT
PORT ddr_clke = ddr_clke, DIR = OUT
PORT ddr_csn = ddr_csn, DIR = OUT
PORT ddr_rasn = ddr_rasn, DIR = OUT
PORT ddr_casn = ddr_casn, DIR = OUT
PORT ddr_wen = ddr_wen, DIR = OUT
PORT ddr_dqm = ddr_dqm, DIR = OUT, VEC = [0:1]
PORT ddr_bankaddr = ddr_bankaddr, DIR = OUT, VEC = [0:1]
PORT ddr_addr = ddr_addr, DIR = OUT, VEC = [0:12]
PORT ddr_dq = ddr_dq, DIR = INOUT, VEC = [0:15]
PORT ddr_dqs = ddr_dqs, DIR = INOUT, VEC = [0:1]

PORT ETH_COL = ETH_COL, DIR = IN
PORT ETH_CRS = ETH_CRS, DIR = IN
PORT ETH_MDC = ETH_MDC, DIR = IN
PORT ETH_MDIO = ETH_MDIO, DIR = IN
PORT ETH_RXC = ETH_RXC, DIR = IN
PORT ETH_RXD = ETH_RXD, DIR = IN, VEC = [3:0]
PORT ETH_RXDV = ETH_RXDV, DIR = IN
PORT ETH_RXER = ETH_RXER, DIR = IN
PORT ETH_TXC = ETH_TXC, DIR = IN
PORT ETH_TXD = ETH_TXD, DIR = OUT, VEC = [3:0]
PORT ETH_TXEN = ETH_TXEN, DIR = OUT
PORT ETH_TXER = ETH_TXER, DIR = OUT
PORT PHY_RESETn = PHY_RESETn, DIR = OUT
# Sub Components
BEGIN microblaze
 PARAMETER INSTANCE = microblaze
 PARAMETER HW_VER = 2.00.a
 PORT CLK = sys_clk

 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DEBUG_ENABLED = 0 #1
 PARAMETER C_NUMBER_OF_PC_BRK = 0 #2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0 #2
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0 #2
 PARAMETER C_USE_DIV = 1

 PARAMETER C_USE_ICACHE = 0
 PARAMETER C_ICACHE_BASEADDR  = 0x80000000
 PARAMETER C_ICACHE_HIGHADDR  = 0x80FFFFFF
 PARAMETER C_CACHE_BYTE_SIZE  = 16384

 PARAMETER C_USE_DCACHE = 0
 PARAMETER C_DCACHE_BASEADDR  = 0x80000000
 PARAMETER C_DCACHE_HIGHADDR  = 0x80FFFFFF
 PARAMETER C_DCACHE_BYTE_SIZE = 16384

 PORT INTERRUPT = interrupt
 BUS_INTERFACE DLMB = d_lmb_v10
 BUS_INTERFACE ILMB = i_lmb_v10
 BUS_INTERFACE DOPB = d_opb_v20
 BUS_INTERFACE IOPB = d_opb_v20
END

# inverter to convert active low sys_rstn to active high sys_rst
BEGIN my_inverter
 PARAMETER INSTANCE = rst_inverter
 PORT I = sys_rstn
 PORT O = sys_rst
END

BEGIN ddr_clk_gen
 PARAMETER INSTANCE = my_ddr_clk_gen
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLKIN_PERIOD_NS = 15.0     # 66mhz internal clock
 PORT CLK_IN = clk66mhz			# 66mhz "external" clock
 PORT CLK_RST = sys_rst             	# tie DCM reset to system reset (active low)
 PORT DDR_CLK_FB = ddr_clk_fb           # feedback from outside
 PORT CLK0 = sys_clk                    # drive system clock with this one
 PORT CLK90 = sys_clk_90                # 90 deg phase shifted system clock
 PORT DDR_CLK_90 = ddr_clk_90           # external feedback 90 deg phase shift
 #PORT CORE_DCM_LOCKED = core_dcm_locked
 #PORT DDR_DCM_LOCKED = ddr_dcm_locked
END

BEGIN opb_ddr
 PARAMETER INSTANCE = ddr_controller
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_OPB_CLK_PERIOD_PS = 15000          # 100mhz clock
 PARAMETER C_INCLUDE_BURST_SUPPORT = 0
 PARAMETER C_DQS_PULLUPS = 1
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_DDR_TMRD = 15000
 PARAMETER C_DDR_TWR = 15000
 PARAMETER C_DDR_TWTR = 1
 PARAMETER C_DDR_TRAS = 40000
 PARAMETER C_DDR_TRC = 65000
 PARAMETER C_DDR_TRFC = 75000
 PARAMETER C_DDR_TRCD = 20000
 PARAMETER C_DDR_TRRD = 15000
 PARAMETER C_DDR_TREFC = 70000000
 PARAMETER C_DDR_TREFI = 7800000
 PARAMETER C_DDR_TRP = 20000
 PARAMETER C_DDR_CAS_LAT = 2
 PARAMETER C_DDR_DWIDTH = 16
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 9
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_BASEADDR = 0x80000000
 PARAMETER C_HIGHADDR = 0x80FFFFFF
 PORT OPB_Clk = sys_clk                         # system clock
 PORT Clk90_in = sys_clk_90                     # phase shifted sys_clk
 PORT DDR_Clk90_in = ddr_clk_90                 # phase shifted feedback clk
 PORT DDR_Clk = ddr_clk                         # output clocks
 PORT DDR_Clkn = ddr_clkn                       # inverted clock
 PORT DDR_CKE = ddr_clke
 PORT DDR_CSn = ddr_csn
 PORT DDR_RASn = ddr_rasn
 PORT DDR_CASn = ddr_casn
 PORT DDR_WEn = ddr_wen
 PORT DDR_DM = ddr_dqm
 PORT DDR_BankAddr = ddr_bankaddr
 PORT DDR_Addr = ddr_addr
 PORT DDR_DQ = ddr_dq
 PORT DDR_DQS = ddr_dqs
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN opb_memcon
 PARAMETER INSTANCE = system_memcon
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPB_CLOCK_PERIOD_PS = 15000
 PARAMETER C_NUM_BANKS_MEM = 2
 PARAMETER C_BASEADDR = 0xffff0000
 PARAMETER C_HIGHADDR = 0xffff00ff
 PARAMETER C_MEM0_BASEADDR = 0xffe00000
 PARAMETER C_MEM0_HIGHADDR = 0xffefffff
 PARAMETER C_MEM1_BASEADDR = 0xff000000
 PARAMETER C_MEM1_HIGHADDR = 0xff7fffff
 PORT Mem_CEN = sram_cen
 PORT Mem_A = sram_addr
 PORT Mem_BEN = sram_ben
 PORT Mem_DQ = sram_data
 PORT Mem_OEN = sram_oen
 PORT Mem_WEN = sram_wen
 PORT OPB_Clk = sys_clk
 PORT Mem_RPN = sram_rst
 PORT Mem_Status_Intrpt = 
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = console_uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_CLK_FREQ = 66_666_667
 PARAMETER C_BASEADDR = 0xFFFF2000
 PARAMETER C_HIGHADDR = 0xFFFF20FF
 PORT Interrupt = console_uart_interrupt
 PORT OPB_Clk = sys_clk
 PORT RX = console_uart_rx
 PORT TX = console_uart_tx
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = debug_uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_CLK_FREQ = 66_666_667
 PARAMETER C_BAUDRATE = 230400
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_BASEADDR = 0xFFFF4000
 PARAMETER C_HIGHADDR = 0xFFFF40FF
 PORT Interrupt = debug_uart_interrupt
 PORT OPB_Clk = sys_clk
 PORT RX = debug_uart_rx
 PORT TX = debug_uart_tx
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN opb_intc
 PARAMETER INSTANCE = system_intc
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0xffff3000
 PARAMETER C_HIGHADDR = 0xffff30ff
 PORT Irq = interrupt 
 PORT OPB_Clk = sys_clk
 PORT Intr = ethernet_interrupt & debug_uart_interrupt & console_uart_interrupt & timer_interrupt 
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN opb_timer
 PARAMETER INSTANCE = system_timer
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffff1000
 PARAMETER C_HIGHADDR = 0xffff10ff
 PORT OPB_Clk = sys_clk
 PORT Interrupt = timer_interrupt
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN opb_gpio
 PARAMETER INSTANCE = system_gpio
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xffff5000
 PARAMETER C_HIGHADDR = 0xffff50ff
 PORT GPIO_IO = gpio
 PORT OPB_Clk = sys_clk
 BUS_INTERFACE SOPB = d_opb_v20
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = d_lmb_bram_if_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003FFF
 PORT LMB_Clk = sys_clk
 BUS_INTERFACE SLMB = d_lmb_v10
 BUS_INTERFACE BRAM_PORT = conn_0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = i_lmb_bram_if_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00003FFF
 PORT LMB_Clk = sys_clk
 BUS_INTERFACE SLMB = i_lmb_v10
 BUS_INTERFACE BRAM_PORT = conn_1
END

BEGIN bram_block
 PARAMETER INSTANCE = bram
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MEMSIZE = 16384
 BUS_INTERFACE PORTA = conn_0
 BUS_INTERFACE PORTB = conn_1
END

BEGIN opb_v20
 PARAMETER INSTANCE = d_opb_v20
 PARAMETER HW_VER = 1.10.b
 PORT OPB_Clk = sys_clk
 PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
 PARAMETER INSTANCE = i_lmb_v10
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk
 PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
 PARAMETER INSTANCE = d_lmb_v10
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk
 PORT SYS_Rst = sys_rst
END

BEGIN my_dcm
 PARAMETER INSTANCE = system_dcm
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLKIN_PERIOD_NS = 10.0
 PARAMETER C_DIVISOR = 3
 PARAMETER C_INBUFFER = TRUE
 PARAMETER C_MULTIPLIER = 2
 PARAMETER C_OUTBUFFER = TRUE
 PORT CLK_IN = ext_clk			# external clock input pin
 PORT CLK_RST = net_gnd
 PORT CLK_0 = clk_fb_o
 PORT CLK_FB = clk_fb_i
 PORT CLK_FX = clk66mhz			# input to ddr_clk_gen module
END

BEGIN my_bufg
 PARAMETER INSTANCE = dcm_feedback_bufg
 PORT I = clk_fb_o
 PORT O = clk_fb_i
END

# BEGIN opb_mdm
# PARAMETER INSTANCE = mdm
# PARAMETER HW_VER = 1.00.c
# PARAMETER C_BASEADDR = 0xffff7000
# PARAMETER C_HIGHADDR = 0xffff70ff
# PORT OPB_Clk = sys_clk
# BUS_INTERFACE SOPB = d_opb_v20
#END

BEGIN opb_ethernet
 PARAMETER INSTANCE = ether
 PARAMETER C_FAMILY = virtex2
 PARAMETER HW_VER = 1.00.k
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_DMA_INTR_COALESCE = 1
 PARAMETER C_OPB_CLK_PERIOD_PS = 15000
 PARAMETER C_BASEADDR = 0xC0000000
 PARAMETER C_HIGHADDR = 0xC0003FFF
 PORT OPB_Clk = sys_clk
 PORT OPB_Rst = sys_rst
 PORT PHY_col = ETH_COL
 PORT PHY_crs = ETH_CRS
 PORT PHY_Mii_clk = ETH_MDC
 PORT PHY_Mii_data = ETH_MDIO
 PORT PHY_rx_clk = ETH_RXC
 PORT PHY_rx_data = ETH_RXD
 PORT PHY_dv = ETH_RXDV
 PORT PHY_rx_er = ETH_RXER
 PORT PHY_tx_clk = ETH_TXC
 PORT PHY_tx_data = ETH_TXD
 PORT PHY_tx_en = ETH_TXEN
 PORT PHY_tx_er = ETH_TXER
 PORT PHY_rst_n = PHY_RESETn
 PORT Freeze = net_gnd
 PORT IP2INTC_Irpt = ethernet_interrupt
 BUS_INTERFACE MSOPB = d_opb_v20
END

######################################################
# Clock Period Constraints
######################################################
NET "sys_clk" TNM_NET = "sys_clk";
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 15 ns HIGH 50 %;
NET "sys_clk_90" TNM_NET = "sys_clk_90";
TIMESPEC "TS_CLK90" = PERIOD "sys_clk_90" 15 ns HIGH 50% ;
TIMESPEC "TSCLK2CLK90" = FROM "sys_clk" TO "sys_clk_90" 3 ns;
NET "ddr_clk_90" TNM_NET = "ddr_clk_90";
TIMESPEC "TS_ddr_clk_90" = PERIOD "ddr_clk_90" 15 ns HIGH 50 %;

######################################################
# IO Standards constraints
######################################################
NET "ddr_dqs<0>" IOSTANDARD=SSTL2_I;
NET "ddr_dqs<0>" PULLDOWN;
NET "ddr_dqs<1>" IOSTANDARD=SSTL2_I;
NET "ddr_dqs<1>" PULLDOWN;

NET "ddr_dq<0>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<1>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<2>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<3>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<4>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<5>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<6>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<7>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<8>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<9>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<10>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<11>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<12>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<13>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<14>" IOSTANDARD=SSTL2_I;
NET "ddr_dq<15>" IOSTANDARD=SSTL2_I;

NET "ddr_addr<0>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<1>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<2>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<3>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<4>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<5>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<6>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<7>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<8>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<9>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<10>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<11>" IOSTANDARD=SSTL2_I;
NET "ddr_addr<12>" IOSTANDARD=SSTL2_I;

NET "ddr_clk_fb" IOSTANDARD=SSTL2_I;
NET "ddr_clk" IOSTANDARD=SSTL2_I;
NET "ddr_clkn" IOSTANDARD=SSTL2_I;
NET "ddr_dqm<1>" IOSTANDARD=SSTL2_I;
NET "ddr_dqm<0>" IOSTANDARD=SSTL2_I;
NET "ddr_bankaddr<1>" IOSTANDARD=SSTL2_I;
NET "ddr_bankaddr<0>" IOSTANDARD=SSTL2_I;
NET "ddr_casn" IOSTANDARD=SSTL2_I;
NET "ddr_clke" IOSTANDARD=SSTL2_I;
NET "ddr_csn" IOSTANDARD=SSTL2_I;
NET "ddr_rasn" IOSTANDARD=SSTL2_I;
NET "ddr_wen" IOSTANDARD=SSTL2_I;

###############################################################################
# Pin Assignments
###############################################################################

# external 100MHz oscillator
NET "ext_clk" LOC = "B11";

# external reset pin (push 2).  Active low
NET "sys_rstn" LOC = "A6";

# stdio uart tx/rx goes to the main board RS232 driver
NET "console_uart_tx" LOC = "A7";
NET "console_uart_rx" LOC = "B7";

# debug uart tx/rx goes to P160 comms board RS232 driver
NET "debug_uart_tx" LOC = "H22";
NET "debug_uart_rx" LOC = "H21";

# sram/flash address pins

# put unused lines on harmless pins
NET "sram_addr<31>" LOC = "H2";
NET "sram_addr<30>" LOC = "H1";
NET "sram_addr<6>" LOC = "J2"; # A22
NET "sram_addr<5>" LOC = "J1"; # A22
NET "sram_addr<4>" LOC = "K1"; # A22
NET "sram_addr<3>" LOC = "K2"; # A22
NET "sram_addr<2>" LOC = "E4"; # A22
NET "sram_addr<1>" LOC = "E3"; # A22
NET "sram_addr<0>" LOC = "F4"; # A22
# now real pins
NET "sram_addr<29>" LOC = "W8";
NET "sram_addr<28>" LOC = "AB6";
NET "sram_addr<27>" LOC = "V8";
NET "sram_addr<26>" LOC = "W7";
NET "sram_addr<25>" LOC = "V9";
NET "sram_addr<24>" LOC = "AA6";
NET "sram_addr<23>" LOC = "V7";
NET "sram_addr<22>" LOC = "AB5";
NET "sram_addr<21>" LOC = "AB18";
NET "sram_addr<20>" LOC = "AA17";
NET "sram_addr<19>" LOC = "Y14";
NET "sram_addr<18>" LOC = "Y15";
NET "sram_addr<17>" LOC = "AB16";
NET "sram_addr<16>" LOC = "AB17";
NET "sram_addr<15>" LOC = "AB15";
NET "sram_addr<14>" LOC = "W14";
NET "sram_addr<13>" LOC = "W13";
NET "sram_addr<12>" LOC = "Y7";
NET "sram_addr<11>" LOC = "Y6";
NET "sram_addr<10>" LOC = "AA16";
NET "sram_addr<9>" LOC = "W6";
NET "sram_addr<8>" LOC = "AA15";
NET "sram_addr<7>" LOC = "W17"; # A22

# data pins
NET "sram_data<31>" LOC = "AA12";
NET "sram_data<30>" LOC = "U14";
NET "sram_data<29>" LOC = "W15";
NET "sram_data<28>" LOC = "Y12";
NET "sram_data<27>" LOC = "Y16";
NET "sram_data<26>" LOC = "AA13";
NET "sram_data<25>" LOC = "Y17";
NET "sram_data<24>" LOC = "W16";
NET "sram_data<23>" LOC = "V12";
NET "sram_data<22>" LOC = "AB13";
NET "sram_data<21>" LOC = "W12";
NET "sram_data<20>" LOC = "V16";
NET "sram_data<19>" LOC = "AB14";
NET "sram_data<18>" LOC = "Y13";
NET "sram_data<17>" LOC = "V13";
NET "sram_data<16>" LOC = "AA14";
NET "sram_data<15>" LOC = "Y8";
NET "sram_data<14>" LOC = "AA7";
NET "sram_data<13>" LOC = "W9";
NET "sram_data<12>" LOC = "U11";
NET "sram_data<11>" LOC = "Y9";
NET "sram_data<10>" LOC = "AB8";
NET "sram_data<9>" LOC = "AB9";
NET "sram_data<8>" LOC = "U13";
NET "sram_data<7>" LOC = "AB7";
NET "sram_data<6>" LOC = "U9";
NET "sram_data<5>" LOC = "U10";
NET "sram_data<4>" LOC = "AA8";
NET "sram_data<3>" LOC = "U12";
NET "sram_data<2>" LOC = "AA9";
NET "sram_data<1>" LOC = "W10";
NET "sram_data<0>" LOC = "Y10";

#and control signals
NET "sram_cen<0>" LOC = "AB12";
NET "sram_cen<1>" LOC = "V10";
NET "sram_wen" LOC = "AA5";
NET "sram_oen" LOC = "V14";
NET "sram_ben<0>" LOC = "G19";
NET "sram_ben<1>" LOC = "H20";
NET "sram_ben<2>" LOC = "G20";
NET "sram_ben<3>" LOC = "H19";
# NET "sram_STS"    LOC = "V6";
NET "sram_rst" LOC = "E18";


# DDR pins.  Watch for endian conversions
# Address first
# DDR Controller signal                   DDR chip pin
NET "ddr_addr<12>" LOC = "B18";         # DDR_A0
NET "ddr_addr<11>" LOC = "A18";
NET "ddr_addr<10>" LOC = "B17";
NET "ddr_addr<9>" LOC = "A17";
NET "ddr_addr<8>" LOC = "N17";
NET "ddr_addr<7>" LOC = "P18";
NET "ddr_addr<6>" LOC = "P17";
NET "ddr_addr<5>" LOC = "M18";
NET "ddr_addr<4>" LOC = "M19";
NET "ddr_addr<3>" LOC = "M20";
NET "ddr_addr<2>" LOC = "A19";
NET "ddr_addr<1>" LOC = "N18";
NET "ddr_addr<0>" LOC = "N20";          # DDR_A12

# data
NET "ddr_dq<15>" LOC = "Y21";           # DQ_0
NET "ddr_dq<14>" LOC = "Y22";
NET "ddr_dq<13>" LOC = "W21";
NET "ddr_dq<12>" LOC = "V21";
NET "ddr_dq<11>" LOC = "V22";
NET "ddr_dq<10>" LOC = "U21";
NET "ddr_dq<9>" LOC = "U22";
NET "ddr_dq<8>" LOC = "T21";
NET "ddr_dq<7>" LOC = "R20";
NET "ddr_dq<6>" LOC = "R19";
NET "ddr_dq<5>" LOC = "T20";
NET "ddr_dq<4>" LOC = "T19";
NET "ddr_dq<3>" LOC = "U19";
NET "ddr_dq<2>" LOC = "V20";
NET "ddr_dq<1>" LOC = "V19";
NET "ddr_dq<0>" LOC = "W20";            # DQ_15

NET "ddr_bankaddr<1>" LOC = "M21";      # BS_0
NET "ddr_bankaddr<0>" LOC = "B19";      # BS_1
NET "ddr_dqm<1>" LOC = "R21";            # LDM
NET "ddr_dqm<0>" LOC = "T22";            # UDM
NET "ddr_dqs<1>" LOC = "P20";           # LDQS
NET "ddr_dqs<0>" LOC = "P19";           # UDQS
NET "ddr_csn" LOC = "N22";
NET "ddr_rasn" LOC = "N21";
NET "ddr_casn" LOC = "P21";
NET "ddr_wen" LOC = "R22";
NET "ddr_clke" LOC = "N19";

NET "ddr_clk" LOC = "D12";
NET "ddr_clkn" LOC = "E12";
NET "ddr_clk_fb" LOC = "F13";

# gpio
# left LEDs
# No 8th segment, so left unconnected
NET "gpio<0>" LOC = "D9";
NET "gpio<1>" LOC = "C9";
NET "gpio<2>" LOC = "F11";
NET "gpio<3>" LOC = "F9";
NET "gpio<4>" LOC = "F10";
NET "gpio<5>" LOC = "D10";
NET "gpio<6>" LOC = "C10";

#right LEDs
# No 8th segment, so left unconnected
NET "gpio<8>" LOC = "B9";
NET "gpio<9>" LOC = "A8";
NET "gpio<10>" LOC = "B8";
NET "gpio<11>" LOC = "E7";
NET "gpio<12>" LOC = "E8";
NET "gpio<13>" LOC = "E10";
NET "gpio<14>" LOC = "E9";

# user LED, use as power indicator
NET "gpio<15>" LOC = "A9";

#DIP switches
NET "gpio<16>" LOC = "C6"; # sw 8
NET "gpio<17>" LOC = "D6"; # sw 7
NET "gpio<18>" LOC = "A5"; # ...
NET "gpio<19>" LOC = "B5";
NET "gpio<20>" LOC = "C5";
NET "gpio<21>" LOC = "C4";
NET "gpio<22>" LOC = "A4"; # sw 2
NET "gpio<23>" LOC = "B4"; # sw 1

# Ethernet Pin constraints
NET "ETH_TXC"    LOC = "C11";    #LIOA35(.2v5)
NET "ETH_RXC"    LOC = "D11";    #LIOA33(.2v5)
NET "ETH_CRS"    LOC = "J19";    #LIOB25
NET "ETH_RXDV"   LOC = "D22";     #LIOA17(.2v5)
NET "ETH_RXD<0>"    LOC = "E21"; #LIOB17
NET "ETH_RXD<1>"    LOC = "E22"; #LIOB16
NET "ETH_RXD<2>"    LOC = "F21"; #LIOA15
NET "ETH_RXD<3>"    LOC = "F22"; #LIOB15
NET "ETH_COL"    LOC = "J20";    #LIOB24
NET "ETH_RXER" LOC = "C22";      #LIOB19
NET "ETH_TXEN"   LOC = "L19";    #LIOB21
NET "ETH_TXER" LOC = "C21";       #LIOA19(.2v5)
NET "ETH_TXD<0>"    LOC = "L20"; #LIOA21(.2v5)
NET "ETH_TXD<1>"    LOC = "K18"; #LIOB22
NET "ETH_TXD<2>"    LOC = "K20"; #LIOB23
NET "ETH_TXD<3>"    LOC = "K19"; #LIOA23(.2v5)
NET "ETH_MDC" LOC = "G21";       #LIOB14
NET "PHY_RESETn" LOC = "K17";    #LIOB31
NET "ETH_MDIO" LOC = "G22";      #LIOA13

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