Re: [microblaze-uclinux] Wrong port direction of sys_rst; possibleerror in mbvanilla_ddr_2.00.b?

[John Williams <jwilliams@itee.uq.edu.au>]

Hi Günter,

Günter Dannoritzer wrote:
> I tried to implement the mbvanilla_ddr_2.00.b using the EDK 3.2.2. After running the generate netlist command I got a synthesis error with the my_inverter block.
> 
> In the system.mhs file the global ports sys_rstn and sys_rst are both defined as inputs. I changed the direction of sys_rst to an output and the synthesis worked just fine.

This sounds a bit strange - only sys_rstn is a global.  sys_rst is an 
internal signal, declared implicitly by the following

# inverter to convert active low sys_rstn to active high sys_rst
BEGIN my_inverter
  PARAMETER INSTANCE = rst_inverter
  PORT I = sys_rstn
  PORT O = sys_rst
END

I just grabbed the zip file fresh from the website- it looks correct, 
and is generated directly from my internal CVS tree.

So, I'm not sure what you are seeing.  Perhaps try downloading or 
unzipping the package again?  It should work out of the box with EDK3.2.2...

Sorry this isn't much help!  Please let me know what you find.

Regards,

John

PS In my opinion, this implicit internal signal declaration is an 
unneccessary weakness of platgen and the MHS format.  Any signal 
referred to in a "PORT" statement within a BEGIN/END block implicitly 
defines a signal.   This means that simple typos and brainfarts can 
generate really cryptic errors, much later in the synthesis process.  As 
anyone who used to program in Basic (Fortran too?) will probably 
remember, implicit declarations are a bad thing!

Ideally it would be required to explicitly declare all internal signals 
before referencing them, making MHS files much more robust against 
simple errors.



___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/