[microblaze-uclinux] [patch] microblaze cache handling

[John Williams <jwilliams@itee.uq.edu.au>]

Hi Greg/David,

Some changes to include/asm-microblaze/pgalloc.h, to make cache handling 
much less conservative.  dcache flushing is removed, since microblaze 
has a write-through cache, and icache_flush_XXX routines now only flushe 
the necessary range, rather than the entire cache.

Significant performance improvements result :)

Thanks,

John
Index: io.h
===================================================================
RCS file: /var/cvs/uClinux-2.4.x/include/asm-microblaze/io.h,v
retrieving revision 1.5
diff -u -b -B -w -p -r1.5 io.h
--- io.h	2003/08/12 01:55:07	1.5
+++ io.h	2003/12/03 06:06:39
@@ -18,10 +18,6 @@
 
 #include <asm/virtconvert.h>
 
-#ifndef __OPTIMIZE__
-#define extern static
-#endif
-
 #define IO_SPACE_LIMIT 0xFFFFFFFF
 
 #define readb(addr) \
@@ -131,9 +127,5 @@ io_outsl (unsigned long port, const void
 #define ioremap_nocache(physaddr, size)		(physaddr)
 #define ioremap_writethrough(physaddr, size)	(physaddr)
 #define ioremap_fullcache(physaddr, size)	(physaddr)
-
-#ifndef __OPTIMIZE__
-#undef extern 
-#endif
 
 #endif /* __MICROBLAZE_IO_H__ */
Index: pgalloc.h
===================================================================
RCS file: /var/cvs/uClinux-2.4.x/include/asm-microblaze/pgalloc.h,v
retrieving revision 1.2
diff -u -b -B -w -p -r1.2 pgalloc.h
--- pgalloc.h	2003/09/22 04:34:25	1.2
+++ pgalloc.h	2003/12/03 06:06:39
@@ -8,18 +8,21 @@
 
 #include <asm/setup.h>
 #include <asm/virtconvert.h>
+#include <asm/page.h>
 
 /*
  * Cache handling functions
  */
 
+/* The following hard-codes some assumptions, and needs to be cleaned up. 
+   We need to get cache-description #defines into xparameters.h at least
+   and use them to drive the code below.
+*/
 extern inline void __flush_cache_all(void)
 {
 #ifdef CONFIG_MICROBLAZE_ICACHE
 	unsigned int i;
-	unsigned int flags;
 
-	save_flags(flags);cli();
 	__disable_icache();
 	__disable_dcache();
 
@@ -29,22 +32,39 @@ extern inline void __flush_cache_all(voi
 		__invalidate_dcache(i+0x80000000);
 	}
 	__enable_icache();
+	__enable_dcache();
+#endif /* CONFIG_MICROBLAZE_ICACHE */
+}
+
+extern inline void __flush_cache_range(unsigned int start, unsigned int end)
+{
+#ifdef CONFIG_MICROBLAZE_ICACHE
+	unsigned int i;
+
+	__disable_icache();
+	__disable_dcache();
+
+	for(i=start;i<end;i+=4)
+	{
+		__invalidate_icache(i);
+		__invalidate_dcache(i);
+	}
+	__enable_icache();
 	__enable_dcache();
-	restore_flags(flags);
 #endif /* CONFIG_MICROBLAZE_ICACHE */
 }
 
 #define flush_cache_all()			__flush_cache_all()
-#define flush_cache_mm(mm)			__flush_cache_all()
-#define flush_cache_range(mm, start, end)	__flush_cache_all()
-#define flush_cache_page(vma, vmaddr)		__flush_cache_all()
-#define flush_page_to_ram(page)			__flush_cache_all()
-#define flush_dcache_page(page)			__flush_cache_all()
-#define flush_icache_range(start, end)		__flush_cache_all()
+#define flush_cache_mm(mm)			do { } while(0)
+#define flush_cache_range(mm, start, end)	do { } while(0)
+#define flush_cache_page(vma, vmaddr)		do { } while(0)
+#define flush_page_to_ram(page)			do { } while(0)
+#define flush_dcache_page(page)			do { } while(0)
+#define flush_icache_range(start, end)		__flush_cache_range(start,end)
 #define flush_icache_user_range(vma,pg,adr,len) __flush_cache_all()
 #define flush_icache_page(vma,pg)		__flush_cache_all()
 #define flush_icache()				__flush_cache_all()
-#define flush_cache_sigtramp(vaddr)		__flush_cache_all()
+#define flush_cache_sigtramp(vaddr)		__flush_cache_range(vaddr,vaddr+4)
 
 /*
  * DAVIDM - the rest of these are just so I can check where they happen