Re: [microblaze-uclinux] Caches

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Hi Eric,

Hansen Eric wrote:

>>this file.  Line 29, change the cache size from 0x8000 to 0x10000 and 
>>you should be right.  This parameter should move into xparameters.h - 
>>I'll do it today and submit it to the CVS! :)
> 
> 
> Funny thing. I have had already set cache size to 0x10000. Id did not
> work.
> But when looking at your MHS from mbvanilla_net_v1_00_a I found one
> thing
> I did not understand... Your memory size on the LMB is 16384, which is
> 4000 in hex.
> Nevertheless you set size to 8000? As we have got 4 times as much memory
> on
> the LMB do we have to set memory size to 20000? Currently I have set it
> to
> 10000.

hmm..  Just looking into it, I'd say that it was an error on my part, 
but a harmless one.  If you look at the Microblaze references on the 
cache implementation, basically the rightmost log2(cache_size) bits are 
used as the cache BRAM lookup address.  By setting the cache sizes too 
large by a factor of 2, i was causing the caches to be invalidated 
twice.  not optimal, but probably not harmful.

So, I think you should be correct with the 0x10000 for a 64K cache..

I did, however, find a different error, which is in my sizing of the 
cache tag bits.  As I see it, the following relationship should be true 
for the caches, to get full coverage:

log2(cacheable_range) = log2(cache_size) + tag_bits

For mbvanilla_net, this gives
tag_bits = log2(16Mb)-log2(16384)
          = 24 - 14
          = 10

For the "new and improved" 32Mbyte mbvanilla, this would be 11 tag bits.

However in the MHS file, I've specified only 9 bits of tag - as I 
understand it, this would cause false hits (and misses) in accesses 
outside the first 8Mbyte... ouch.

I'll look into it and try to clarify.

John

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