Re: [microblaze-uclinux] OT?, Performance

[Goran Bilski <Goran.Bilski@xxxxxxxxxx>]

Hi,

emanuel stiebler wrote:

> Goran Bilski wrote:
>
>> The 100 DMIPS is when running at 125 MHz with the HW divider enabled 
>> and running from BRAM.
>> On a 100 MHz microblaze running from external memory this is what you 
>> can expect.
>> I'm however working on things to improve this but this is the current 
>> fact.
>> So a 150 MHz MicroBlaze in V2P will give you around 50 DMIPS with 
>> external memories.
>> It's also depending on the external memory. A fast SRAM will give you 
>> better values than a SDRAM.
>> A really fast SRAM can improve it quite a lot. But they are expensive.
>
>
> You have any experience what type of SRAM would give the best results,
> for lets say a 8 MByte system ? Any idea what the speedup would be ?

The faster the better but also the more expensive.
Today using SDRAM will give you a latency of 12 clock cycles.
Running at 100 MHz and with 10 ns memory might get you down to around 
4-5 clock cycles.
I'm not sure since I don't have this kind of boards.
The DMIPS number will go up.

Another way is to wait for me to get the new stuff done and tested.

>
>> Another way to improve the numbers is to use the harvard architecute 
>> of MicroBlaze and have 2 OPB busses and two external memories.
>
>
> But we can't support it on the uclinux ...
>
> Cheers,
> emanuel
>
>
>
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