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[microblaze-uclinux] [patch] dos2unix auto-config.in for suzaku

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] [patch] dos2unix auto-config.in for suzaku
From: Yasushi SHOJI <yashi@xxxxxxxxxxxxxxxxx>
Date: Thu, 18 Nov 2004 12:34:44 +0900
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
User-agent: User-Agent: Wanderlust/2.10.1
hi john,

subject says all. here is trivial patch for auto-config.in

best,
--
        yashi
 auto-config.in |  532 ++++++++++++++++++++++++++++-----------------------------
 1 files changed, 266 insertions(+), 266 deletions(-)

Index: linux-suzaku/arch/microblaze/platform/suzaku/auto-config.in
===================================================================
--- linux-suzaku.orig/arch/microblaze/platform/suzaku/auto-config.in	2004-11-15 08:24:57.000000000 +0900
+++ linux-suzaku/arch/microblaze/platform/suzaku/auto-config.in	2004-11-18 12:33:19.243872170 +0900
@@ -1,266 +1,266 @@
-
-
-# Main Memory Settings
-define_hex CONFIG_XILINX_ERAM_START 0x80000000
-define_hex CONFIG_XILINX_ERAM_SIZE 0x01000000
-
-# Lmb Memory Settings
-define_hex CONFIG_XILINX_LMB_BASEADDR 0x00000000
-define_hex CONFIG_XILINX_LMB_SIZE 0x00000800
-
-# System Clock Frequency
-define_int CONFIG_XILINX_CPU_CLOCK_FREQ 51609600
-
-# Definitions for MICROBLAZE0
-define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze0
-define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
-define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
-define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
-define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
-define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
-define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 1
-define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 1
-define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
-define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
-define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 4
-define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
-define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
-define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
-define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
-define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x80000000
-define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x80FFFFFF
-define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
-define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
-define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 11
-define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
-define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x80000000
-define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x81FFFFFF
-define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0
-define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
-define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 11
-define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 16384
-define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 2.10.a
-
-# Definitions for LMB_BRAM_IF_CNTLR_0
-define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmbcntlr
-define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
-define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
-define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x80000000
-define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
-define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
-define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmbcntlr
-define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b
-
-# Definitions for LMB_BRAM_IF_CNTLR_1
-define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmbcntlr
-define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
-define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
-define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x80000000
-define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
-define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
-define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmbcntlr
-define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b
-
-# No. of instances for LMB_BRAM_IF_CNTLR
-define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
-
-# Definitions for EMC_0
-define_string CONFIG_XILINX_EMC_0_INSTANCE sramflash
-define_string CONFIG_XILINX_EMC_0_NUM_BANKS_MEM 2
-define_string CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS 0
-define_hex CONFIG_XILINX_EMC_0_BASEADDR 0xFFFF0000
-define_hex CONFIG_XILINX_EMC_0_HIGHADDR 0xFFFF01FF
-define_hex CONFIG_XILINX_EMC_0_MEM0_BASEADDR 0xFFE00000
-define_hex CONFIG_XILINX_EMC_0_MEM0_HIGHADDR 0xFFEFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM1_BASEADDR 0xFF000000
-define_hex CONFIG_XILINX_EMC_0_MEM1_HIGHADDR 0xFF7FFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM2_BASEADDR 0xFFFFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM2_HIGHADDR 0x00000000
-define_hex CONFIG_XILINX_EMC_0_MEM3_BASEADDR 0xFFFFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM3_HIGHADDR 0x00000000
-define_hex CONFIG_XILINX_EMC_0_MEM4_BASEADDR 0xFFFFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM4_HIGHADDR 0x00000000
-define_hex CONFIG_XILINX_EMC_0_MEM5_BASEADDR 0xFFFFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM5_HIGHADDR 0x00000000
-define_hex CONFIG_XILINX_EMC_0_MEM6_BASEADDR 0xFFFFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM6_HIGHADDR 0x00000000
-define_hex CONFIG_XILINX_EMC_0_MEM7_BASEADDR 0xFFFFFFFF
-define_hex CONFIG_XILINX_EMC_0_MEM7_HIGHADDR 0x00000000
-define_int CONFIG_XILINX_EMC_0_MEM0_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM1_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM2_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM3_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM4_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM5_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM6_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MEM7_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH 32
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0 0
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1 0
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2 1
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3 1
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_4 1
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_5 1
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_6 1
-define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_7 1
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_0 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_0 150000
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_0 55000
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_0 70000
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_0 150000
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_0 55000
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_0 15000
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_0 35000
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_1 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_1 150000
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_1 55000
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_1 70000
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_1 150000
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_1 55000
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_1 15000
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_1 35000
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_2 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_2 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_2 0
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_2 0
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_2 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_2 0
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_2 0
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_2 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_3 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_3 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_3 0
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_3 0
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_3 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_3 0
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_3 0
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_3 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_4 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_4 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_4 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_4 0
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_4 0
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_4 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_4 0
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_4 0
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_4 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_5 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_5 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_5 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_5 0
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_5 0
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_5 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_5 0
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_5 0
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_5 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_6 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_6 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_6 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_6 0
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_6 0
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_6 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_6 0
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_6 0
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_6 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_7 0
-define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_7 2
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_7 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_7 0
-define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_7 0
-define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_7 0
-define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_7 0
-define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_7 0
-define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_7 0
-define_int CONFIG_XILINX_EMC_0_OPB_DWIDTH 32
-define_int CONFIG_XILINX_EMC_0_OPB_AWIDTH 32
-define_int CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS 15000
-define_int CONFIG_XILINX_EMC_0_DEV_BLK_ID 1
-define_int CONFIG_XILINX_EMC_0_DEV_MIR_ENABLE 1
-define_string CONFIG_XILINX_EMC_0_INSTANCE sramflash
-define_string CONFIG_XILINX_EMC_0_HW_VER 1.10.b
-
-# No. of instances for EMC
-define_int CONFIG_XILINX_EMC_NUM_INSTANCES 1
-
-# Definitions for UARTLITE_0
-define_string CONFIG_XILINX_UARTLITE_0_INSTANCE consoleuart
-define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0xFFFF2000
-define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0xFFFF20FF
-define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
-define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
-define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
-define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 51609600
-define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200
-define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
-define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
-define_string CONFIG_XILINX_UARTLITE_0_INSTANCE consoleuart
-define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
-define_int CONFIG_XILINX_UARTLITE_0_IRQ 1
-
-# No. of instances for UARTLITE
-define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
-
-# Definitions for INTC_0
-define_string CONFIG_XILINX_INTC_0_INSTANCE systemintc
-define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
-define_int CONFIG_XILINX_INTC_0_Y 0
-define_int CONFIG_XILINX_INTC_0_X 0
-define_string CONFIG_XILINX_INTC_0_U_SET intc
-define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
-define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
-define_hex CONFIG_XILINX_INTC_0_BASEADDR 0xFFFF3000
-define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0xFFFF30FF
-define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
-define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000006
-define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000006
-define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000009
-define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
-define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
-define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
-define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
-define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
-define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
-define_string CONFIG_XILINX_INTC_0_INSTANCE systemintc
-define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c
-
-# No. of instances for INTC
-define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
-
-# Definitions for TIMER_0
-define_string CONFIG_XILINX_TIMER_0_INSTANCE systemtimer
-define_string CONFIG_XILINX_TIMER_0_FAMILY spartan3
-define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
-define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
-define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
-define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
-define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
-define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
-define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
-define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
-define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0xFFFF1000
-define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0xFFFF10FF
-define_string CONFIG_XILINX_TIMER_0_INSTANCE systemtimer
-define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
-define_int CONFIG_XILINX_TIMER_0_IRQ 0
-
-# No. of instances for TIMER
-define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
-
-# Definitions for GPIO_0
-define_string CONFIG_XILINX_GPIO_0_INSTANCE systemgpio
-define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0xFFFFA000
-define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0xFFFFA0FF
-define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
-define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
-define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 24
-define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
-define_string CONFIG_XILINX_GPIO_0_INSTANCE systemgpio
-define_string CONFIG_XILINX_GPIO_0_HW_VER 1.00.a
-
-# No. of instances for GPIO
-define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1
-
+
+
+# Main Memory Settings
+define_hex CONFIG_XILINX_ERAM_START 0x80000000
+define_hex CONFIG_XILINX_ERAM_SIZE 0x01000000
+
+# Lmb Memory Settings
+define_hex CONFIG_XILINX_LMB_BASEADDR 0x00000000
+define_hex CONFIG_XILINX_LMB_SIZE 0x00000800
+
+# System Clock Frequency
+define_int CONFIG_XILINX_CPU_CLOCK_FREQ 51609600
+
+# Definitions for MICROBLAZE0
+define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze0
+define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
+define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
+define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
+define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
+define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
+define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 1
+define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 1
+define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
+define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
+define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 4
+define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
+define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
+define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
+define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
+define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x80000000
+define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x80FFFFFF
+define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
+define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
+define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 11
+define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
+define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x80000000
+define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x81FFFFFF
+define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0
+define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
+define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 11
+define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 16384
+define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 2.10.a
+
+# Definitions for LMB_BRAM_IF_CNTLR_0
+define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmbcntlr
+define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
+define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
+define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x80000000
+define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
+define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
+define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmbcntlr
+define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b
+
+# Definitions for LMB_BRAM_IF_CNTLR_1
+define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmbcntlr
+define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
+define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
+define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x80000000
+define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
+define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
+define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmbcntlr
+define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b
+
+# No. of instances for LMB_BRAM_IF_CNTLR
+define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
+
+# Definitions for EMC_0
+define_string CONFIG_XILINX_EMC_0_INSTANCE sramflash
+define_string CONFIG_XILINX_EMC_0_NUM_BANKS_MEM 2
+define_string CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS 0
+define_hex CONFIG_XILINX_EMC_0_BASEADDR 0xFFFF0000
+define_hex CONFIG_XILINX_EMC_0_HIGHADDR 0xFFFF01FF
+define_hex CONFIG_XILINX_EMC_0_MEM0_BASEADDR 0xFFE00000
+define_hex CONFIG_XILINX_EMC_0_MEM0_HIGHADDR 0xFFEFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM1_BASEADDR 0xFF000000
+define_hex CONFIG_XILINX_EMC_0_MEM1_HIGHADDR 0xFF7FFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM2_BASEADDR 0xFFFFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM2_HIGHADDR 0x00000000
+define_hex CONFIG_XILINX_EMC_0_MEM3_BASEADDR 0xFFFFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM3_HIGHADDR 0x00000000
+define_hex CONFIG_XILINX_EMC_0_MEM4_BASEADDR 0xFFFFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM4_HIGHADDR 0x00000000
+define_hex CONFIG_XILINX_EMC_0_MEM5_BASEADDR 0xFFFFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM5_HIGHADDR 0x00000000
+define_hex CONFIG_XILINX_EMC_0_MEM6_BASEADDR 0xFFFFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM6_HIGHADDR 0x00000000
+define_hex CONFIG_XILINX_EMC_0_MEM7_BASEADDR 0xFFFFFFFF
+define_hex CONFIG_XILINX_EMC_0_MEM7_HIGHADDR 0x00000000
+define_int CONFIG_XILINX_EMC_0_MEM0_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM1_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM2_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM3_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM4_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM5_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM6_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MEM7_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH 32
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0 0
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1 0
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2 1
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3 1
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_4 1
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_5 1
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_6 1
+define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_7 1
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_0 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_0 150000
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_0 55000
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_0 70000
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_0 150000
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_0 55000
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_0 15000
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_0 35000
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_1 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_1 150000
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_1 55000
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_1 70000
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_1 150000
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_1 55000
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_1 15000
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_1 35000
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_2 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_2 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_2 0
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_2 0
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_2 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_2 0
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_2 0
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_2 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_3 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_3 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_3 0
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_3 0
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_3 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_3 0
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_3 0
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_3 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_4 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_4 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_4 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_4 0
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_4 0
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_4 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_4 0
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_4 0
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_4 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_5 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_5 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_5 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_5 0
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_5 0
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_5 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_5 0
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_5 0
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_5 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_6 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_6 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_6 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_6 0
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_6 0
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_6 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_6 0
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_6 0
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_6 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_7 0
+define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_7 2
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_7 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_7 0
+define_int CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_7 0
+define_int CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_7 0
+define_int CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_7 0
+define_int CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_7 0
+define_int CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_7 0
+define_int CONFIG_XILINX_EMC_0_OPB_DWIDTH 32
+define_int CONFIG_XILINX_EMC_0_OPB_AWIDTH 32
+define_int CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS 15000
+define_int CONFIG_XILINX_EMC_0_DEV_BLK_ID 1
+define_int CONFIG_XILINX_EMC_0_DEV_MIR_ENABLE 1
+define_string CONFIG_XILINX_EMC_0_INSTANCE sramflash
+define_string CONFIG_XILINX_EMC_0_HW_VER 1.10.b
+
+# No. of instances for EMC
+define_int CONFIG_XILINX_EMC_NUM_INSTANCES 1
+
+# Definitions for UARTLITE_0
+define_string CONFIG_XILINX_UARTLITE_0_INSTANCE consoleuart
+define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0xFFFF2000
+define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0xFFFF20FF
+define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
+define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
+define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
+define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 51609600
+define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 115200
+define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
+define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
+define_string CONFIG_XILINX_UARTLITE_0_INSTANCE consoleuart
+define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
+define_int CONFIG_XILINX_UARTLITE_0_IRQ 1
+
+# No. of instances for UARTLITE
+define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
+
+# Definitions for INTC_0
+define_string CONFIG_XILINX_INTC_0_INSTANCE systemintc
+define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
+define_int CONFIG_XILINX_INTC_0_Y 0
+define_int CONFIG_XILINX_INTC_0_X 0
+define_string CONFIG_XILINX_INTC_0_U_SET intc
+define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
+define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
+define_hex CONFIG_XILINX_INTC_0_BASEADDR 0xFFFF3000
+define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0xFFFF30FF
+define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
+define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000006
+define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000006
+define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000009
+define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
+define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
+define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
+define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
+define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
+define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
+define_string CONFIG_XILINX_INTC_0_INSTANCE systemintc
+define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c
+
+# No. of instances for INTC
+define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
+
+# Definitions for TIMER_0
+define_string CONFIG_XILINX_TIMER_0_INSTANCE systemtimer
+define_string CONFIG_XILINX_TIMER_0_FAMILY spartan3
+define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
+define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
+define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
+define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
+define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
+define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
+define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
+define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
+define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0xFFFF1000
+define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0xFFFF10FF
+define_string CONFIG_XILINX_TIMER_0_INSTANCE systemtimer
+define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
+define_int CONFIG_XILINX_TIMER_0_IRQ 0
+
+# No. of instances for TIMER
+define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
+
+# Definitions for GPIO_0
+define_string CONFIG_XILINX_GPIO_0_INSTANCE systemgpio
+define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0xFFFFA000
+define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0xFFFFA0FF
+define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
+define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
+define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 24
+define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
+define_string CONFIG_XILINX_GPIO_0_INSTANCE systemgpio
+define_string CONFIG_XILINX_GPIO_0_HW_VER 1.00.a
+
+# No. of instances for GPIO
+define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1
+
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