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Kevin, The problem isn't the architecture support per se, but whether you can achieve timing for the DDR in a S3. There is nothing in the core itself that wouldn't prevent you from targeting a S3. Below is an internal solution record which details the steps to re-enable Spartan-III in the OPB DDR controller. This solution record should be made external soon. Matt EDK, DDR, Spartan-3 - ERROR:MDT - opb_ddr (opb_ddr_0) - C:\system.mhs:217 - not supported for architecture 'spartan3'! While the OPB_DDR controller is functionally correct, it did not usually meet internal FPGA timing in Spartan-3 for most DDR RAM chip minimum clock rates. Thus official support for the OPB_DDR was removed from the core. Support for the DDR controller can be re-enabled manually: 1. Copy the existing DDR controller from the EDK install area (typically <i>C:\EDK\hw\XilinxProcessorIPLib\pcores</i>) to a pcores directory. Create a pcores directory in the root of the project if one does not already exist. 2. Modify the <i><myproject>\pcores\opb_ddr_v1_10_a\data\opb_ddr_v2_1_0.mpd</i>. Modify the ARCH_SUPPORT option to contain spartan3, for example: <i>OPTION ARCH_SUPPORT = qrvirtex2:qvirtex2:virtex2:virtex2p:virtex4:spartan3</i> 3. Save the file, restart XPS to reload the core, and rebuild the system 4. Verify that the valid timing constraints are applied to the system, and that those constraints are met in the PAR report or via Timing Analyzer Note that the minimum frequency of the DDR RAM must be met for reliable operation. It may be helpful to choose a RAM device will a lower minimum frequency. Internal Xilinx timing constraints must also be met. Internal Xilinx timing may be improved by enabling the additional pipeline stages in the opb IPIF. To enable additional pipeline registers: 1. Modify the <i><myproject>\pcores\opb_ddr_v1_10_a\hdl\opb_ddr.vhd</i> file to a '7' (maximum) pipeline as below: <i>-- IPIF pipeline model number constant PIPELINE_MODEL : integer := 7;</i> 2. Save the file and regenerate the hardware. Note that there will be additional latency through the OPB_DDR controller. 3. Verify that static timing constraints are being met. A future version of the core will fully support Spartan-3 and DDR SDRAM. The first software containing this fix is scheduled for EDK 7.1 Service Pack 2 Kevin Chen wrote: ___________________________ microblaze-uclinux mailing list microblaze-uclinux@itee.uq.edu.au Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/ |