[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [microblaze-uclinux] error updating bitstream (porting uClinux_auto to Xilinx ML401)
Hi John,
My platform does not have an interrupt controller (I just made it simple
to see if auto_config.in file is generated correctly, I'll include INTC
later if it works fine)
Here you go,
First. MHS file
------------------------------------------
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.11.2
# Tue Jan 18 18:05:15 2005
# Target Board: Xilinx Virtex-II Pro ML310 Evaluation Platform Rev D
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -6
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 8 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 = 256 MB
#
##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_Clk, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_Addr, VEC = [0:12], DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_CSn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DM,
VEC = [0:1], DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_DQS, VEC = [0:1], DIR = INOUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ,
VEC = [0:15], DIR = INOUT
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, VEC =
[0:7], DIR = INOUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT CLK = sys_clk_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT OPB_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0xa0000000
PARAMETER C_HIGHADDR = 0xa000ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_rst_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0xa0010000
PARAMETER C_HIGHADDR = 0xa001ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT RX = fpga_0_RS232_Uart_RX
PORT TX = fpga_0_RS232_Uart_TX
END
BEGIN opb_ddr
PARAMETER INSTANCE = DDR_SDRAM_32Mx64
PARAMETER HW_VER = 1.00.b
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_REG_DIMM = 1
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
# PARAMETER C_NUM_CLK_PAIRS = 2
# PARAMETER C_MEM0_BASEADDR = 0xb0000000
# PARAMETER C_MEM0_HIGHADDR = 0xbfffffff
BUS_INTERFACE SOPB = mb_opb
PORT DDR_Clk90_in = ddr_clk_90_s
PORT Clk90_in = clk_90_s
PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn & 0b0
PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx64_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ
PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx64_DDR_DQS
PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx64_DDR_DM
PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx64_DDR_WEn
PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx64_DDR_RASn
PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx64_DDR_CSn
PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx64_DDR_CKE
PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx64_DDR_CASn
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr
PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx64_DDR_Addr
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.a
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0xa0020000
PARAMETER C_HIGHADDR = 0xa002ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
PORT OPB_Clk = sys_clk_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK180_BUF = TRUE
PARAMETER C_CLK270_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKFB = sys_clk_s
PORT CLK270 = clk_90_n_s
PORT CLK180 = sys_clk_n_s
PORT CLK90 = clk_90_s
PORT CLK0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK270_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 0
PORT LOCKED = dcm_1_lock
PORT RST = dcm_0_lock
PORT CLKFB = dcm_1_FB
PORT CLK0 = dcm_1_FB
PORT CLK270 = ddr_clk_90_n_s
PORT CLK90 = ddr_clk_90_s
PORT CLKIN = ddr_feedback_s
END
-------------------------------------------
Second, MSS file
-------------------------------------------
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdout = RS232_Uart
PARAMETER stdin = RS232_Uart
PARAMETER LMB_MEMORY = ilmb_cntlr
PARAMETER MAIN_MEMORY = DDR_SDRAM_32Mx64
PARAMETER main_memory_bank = 0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER XMDSTUB_PERIPHERAL = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = RS232_Uart
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddr
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = DDR_SDRAM_32Mx64
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = LEDs_8Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_1
END
----------------------------------------------
Thanks,
Taeweon
> Hi Taeweon,
>
> Taeweon Suh wrote:
>> Hi John
>>
>> I am Taeweon and faced the same problem.
>> So, tried with your experimental patch and still failed.
>> Now, OS section of my mss file looks like the below.
>>
>> BEGIN OS
>> PARAMETER OS_NAME = uclinux
>> PARAMETER OS_VER = 1.00.a
>> PARAMETER PROC_INSTANCE = microblaze_0
>> PARAMETER stdout = RS232_Uart
>> PARAMETER stdin = RS232_Uart
>> PARAMETER LMB_MEMORY = ilmb_cntlr
>> PARAMETER MAIN_MEMORY = DDR_SDRAM_32Mx64
>> PARAMETER main_memory_bank = 0
>> END
>
> Can you please post your MHS and MSS files? Prefereably just cut and
> paste their contents inline into the email, so I don't have to save them
> as attachments and launch an external editor.
>
> Thanks,
>
> John
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@itee.uq.edu.au
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive :
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
----------------------------------------------
Taeweon Suh
Ph.D. Candidate
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia USA
Lab: CoC345
Tel: +1-404-385-6273
E-mail: suhtw@ece.gatech.edu
----------------------------------------------
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/