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Re: [microblaze-uclinux] error updating bitstream (porting uClinux_auto to Xilinx ML401)
Hi John,
I added the INTC, but still got error messages.
I guess the message is somewhat related to flash memory setting.
Your tcl and mld files actually created the memu for flash memory.
Is it mandatory to include flash controller like the interrupt controller?
The following is the error message and MHS, MSS files.
Thanks for your effort.
Running generate for OS'es, Drivers and Libraries ...
#--------------------------------------
# uClinux BSP generate...
#--------------------------------------
ERROR:MDT - xget_handle 37365040 ipinst none peripheral : xget_handle: Ip
instance none not found
ERROR:MDT - ERROR FROM TCL:- uclinux () -
while executing
"xget_handle $processor_handle "ipinst" $ipinst_name "peripheral""
(procedure "xget_sw_ipinst_handle_from_processor" line 2)
invoked from within
"xget_sw_ipinst_handle_from_processor $proc_handle $flash_mem"
(procedure "::sw_uclinux_v1_00_a::generate" line 50)
invoked from within
"::sw_uclinux_v1_00_a::generate 36535816"
WARNING: The parameter USE_DCR for the intc driver has been deprecated.
Any reference to this parameter in the MSS file will be ignored.
define_config_file: XNullHandler
Copying Library Files ...
ERROR:MDT - Error while running "generate" for processor microblaze_0...
make: *** [microblaze_0/lib/libxil.a] Error 2
Done.
MHS file
---------------------------------------
#
##############################################################################
#
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.12.3
#
# Fri Jan 28 10:45:17 2005
#
# Target Board: Xilinx Virtex-II Pro ML310 Evaluation Platform Rev D
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -6
#
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 8 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 = 256 MB
#
#
##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_Clk, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_Addr, DIR = OUTPUT, VEC = [0:12]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr, DIR = OUTPUT, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_CASn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_CKE, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_CSn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_RASn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_WEn, DIR = OUTPUT
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DM,
DIR = OUTPUT, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin =
fpga_0_DDR_SDRAM_32Mx64_DDR_DQS, DIR = INOUT, VEC = [0:1]
PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ,
DIR = INOUT, VEC = [0:15]
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR =
INOUT, VEC = [0:7]
PORT fpga_0_ORGate_1_Res_pin = fpga_0_ORGate_1_Res, DIR = OUTPUT
PORT fpga_0_ORGate_1_Res_1_pin = fpga_0_ORGate_1_Res, DIR = OUTPUT
PORT fpga_0_ORGate_1_Res_2_pin = fpga_0_ORGate_1_Res, DIR = OUTPUT
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT CLK = sys_clk_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT Interrupt = Interrupt
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0xa0010000
PARAMETER C_HIGHADDR = 0xa001ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0xa0020000
PARAMETER C_HIGHADDR = 0xa002ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Interrupt = RS232_Uart_Interrupt
PORT RX = fpga_0_RS232_Uart_RX
PORT TX = fpga_0_RS232_Uart_TX
END
BEGIN opb_ddr
PARAMETER INSTANCE = DDR_SDRAM_32Mx64
PARAMETER HW_VER = 1.10.a
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_REG_DIMM = 1
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_NUM_CLK_PAIRS = 2
PARAMETER C_MEM0_BASEADDR = 0xb0000000
PARAMETER C_MEM0_HIGHADDR = 0xbfffffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx64_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx64_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx64_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx64_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx64_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx64_DDR_WEn
PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx64_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx64_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx64_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn & 0b0
PORT Clk90_in = clk_90_s
PORT Clk90_in_n = clk_90_n_s
PORT OPB_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0xa0030000
PARAMETER C_HIGHADDR = 0xa003ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT IP2INTC_Irpt = LEDs_8Bit_IP2INTC_Irpt
PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xa0000000
PARAMETER C_HIGHADDR = 0xa000ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = Interrupt
PORT Intr = RS232_Uart_Interrupt & LEDs_8Bit_IP2INTC_Irpt
END
BEGIN util_reduced_logic
PARAMETER INSTANCE = ORGate_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPERATION = or
PARAMETER C_SIZE = 2
PORT Op1 = sys_rst_s & 0b0
PORT Res = fpga_0_ORGate_1_Res
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK180_BUF = TRUE
PARAMETER C_CLK270_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLK180 = sys_clk_n_s
PORT CLK270 = clk_90_n_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK270_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK270 = ddr_clk_90_n_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
--------------------------------------------
MSS file
-----------------------------------------------------
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER stdout = RS232_Uart
PARAMETER stdin = RS232_Uart
PARAMETER LMB_MEMORY = ilmb_cntlr
PARAMETER MAIN_MEMORY = DDR_SDRAM_32Mx64
PARAMETER main_memory_bank = 0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER XMDSTUB_PERIPHERAL = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = opbarb
PARAMETER DRIVER_VER = 1.02.a
PARAMETER HW_INSTANCE = mb_opb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = RS232_Uart
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = ddr
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = DDR_SDRAM_32Mx64
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = LEDs_8Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = opb_intc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ORGate_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dcm_1
END
--------------------------------------------------------
Taeweon
> Hi Taewon,
>
> Taeweon Suh wrote:
>
>> My platform does not have an interrupt controller
>
> OK, so that will be the cause of the problem. The TCL scripts assume
> that there is an interrupt controller, and probably don't even do any
> error checking in case there is not. Another thing to add to the
> wishlist.
>
> (I just made it simple
>> to see if auto_config.in file is generated correctly, I'll include INTC
>> later if it works fine)
>
> I think you'll have problems with the autoconfig until you add the
> interrupt controller.
>
> Regards,
>
> John
>
> ___________________________
> microblaze-uclinux mailing list
> microblaze-uclinux@itee.uq.edu.au
> Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
> Mailing List Archive :
> http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
----------------------------------------------
Taeweon Suh
Ph.D. Candidate
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia USA
Lab: CoC345
Tel: +1-404-385-6273
E-mail: suhtw@ece.gatech.edu
----------------------------------------------
___________________________
microblaze-uclinux mailing list
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Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/