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Re: [microblaze-uclinux] ML401 update

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] ML401 update
From: John Williams <jwilliams@xxxxxxxxxxxxxx>
Date: Sun, 27 Feb 2005 10:25:48 +1000
In-reply-to: <20050226164946.89121.qmail@web52608.mail.yahoo.com>
References: <20050226164946.89121.qmail@web52608.mail.yahoo.com>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv:1.7.3) Gecko/20040910

Hi Greg,

Greg Miller wrote:

> thanks for the reply (sorry for all the newbie questions).

No worries!

> - I did try the specific Intel Flash option and that is why I am 
> writing; it did not work. Can I look at the code to see what the deal is?

Here's a hint of the problem (from your bootlog):

 > MBVanilla flash probe(0xff000000,8388608,4): 800000 at
 > ff000000

In the drivers/mtd/maps/mbvanilla.c mapping, the address of the flash is 
hard coded.  Take a look, and try to set it to the correct address for 
your flash.  It should be at least detected properly then.

> - FSL Link: Are you using the download commands in Linux not windows? I 
> sent this problem to Xilinx and they could not get it to work iether 
> (FSL link). They told me it was broken for V4 and could not get it to 
> work. They also said they do not know when it will be fixed....

Yeah this is a bit tricky - for the ML401 I'm am doing everything under 
Linux *except* the XMD/JTAG stuff.  There is a special xmd_lx.exe 
distributed by xilinx that works under windows - hopefully they'll 
integrate the hack into the standard xmd build and get it going under 
both windows and linux.

> -The problem is that Linux is not reconizing the PHY... Sometimes. Below 
> it did. However when I plug in a network cable, it crashes. Here is a 
> printout of my boot: That is why I was wondering about the system setup. 
> What is a basic system setup that can be used with net woeking to teest 
> this. with your options, I assume it is supposed to pull an IP address?

I've attached two files - config.linux-2.4.x and config.uclinux-dist. 
These are my current configs for the kernel and dist respectively.  The 
options relating to dhcp are, in the kernel CONFIG_PACKET for the packet 
sock interface, and in the dist, CONFIG_USER_DHCPCD_NEW_DHCPCD, for the 
dhcpcd application.  Note there are a couple of choices for dhcp apps - 
make sure you choose the "new" one.

> If I boot with the cable plugged it, it dies. (Cannot type). If I have 
> the interrupt for the eithernet in above the uart, it will die on 
> boot... It seems to see the carrier however.

Hmm, doesn't sound too healthy - are you doing a full autoconfig setup, 
using the target_dir directive in your MSS file? Or are you hacking on 
the auto-config.in file yourself?  I find it much safer to work with the 
auto-config flow, prevents hard-to-find inconsistencies.

I'll be back working on the ml401 this week, if I learn anything useful 
I'll let you know.

Regards,

John

CONFIG_UCLINUX=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y

CONFIG_EXPERIMENTAL=y

CONFIG_MODULES=y
CONFIG_MICROBLAZE=y

CONFIG_UCLINUX_AUTO=y
HZ=100
CONFIG_XILINX_ERAM_START=0x10000000
CONFIG_XILINX_ERAM_SIZE=0x04000000
CONFIG_XILINX_FLASH_START=0x28000000
CONFIG_XILINX_FLASH_SIZE=0x00800000
CONFIG_XILINX_LMB_START=0x00000000
CONFIG_XILINX_LMB_SIZE=0x00010000
CONFIG_XILINX_CPU_CLOCK_FREQ=100000000
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0"
CONFIG_XILINX_MICROBLAZE0_FAMILY="virtex4"
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0"
CONFIG_XILINX_MICROBLAZE0_D_OPB=1
CONFIG_XILINX_MICROBLAZE0_D_LMB=1
CONFIG_XILINX_MICROBLAZE0_I_OPB=1
CONFIG_XILINX_MICROBLAZE0_I_LMB=1
CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS=0
CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION=0
CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED=1
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK=2
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK=1
CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK=1
CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE=0
CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE=1
CONFIG_XILINX_MICROBLAZE0_FSL_LINKS=1
CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE=32
CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR=0x10000000
CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR=0x13FFFFFF
CONFIG_XILINX_MICROBLAZE0_USE_ICACHE=1
CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR=1
CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS=12
CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE=16384
CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL=0
CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR=0x10000000
CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR=0x13FFFFFF
CONFIG_XILINX_MICROBLAZE0_USE_DCACHE=1
CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR=1
CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG=12
CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE=16384
CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL=0
CONFIG_XILINX_MICROBLAZE0_INSTANCE="microblaze_0"
CONFIG_XILINX_MICROBLAZE0_HW_VER="3.00.a"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE="lmb_bram_if_cntlr_0"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR=0x00000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR=0x0000FFFF
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK=0x38000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE="lmb_bram_if_cntlr_0"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER="1.00.b"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE="lmb_bram_if_cntlr_1"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR=0x00000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR=0x0000FFFF
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK=0x38000000
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH=32
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE="lmb_bram_if_cntlr_1"
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER="1.00.b"
CONFIG_XILINX_MDM_0_INSTANCE="opb_mdm_0"
CONFIG_XILINX_MDM_0_BASEADDR=0xFFFE8000
CONFIG_XILINX_MDM_0_HIGHADDR=0xFFFE80FF
CONFIG_XILINX_MDM_0_OPB_DWIDTH=32
CONFIG_XILINX_MDM_0_OPB_AWIDTH=32
CONFIG_XILINX_MDM_0_FAMILY="virtex4"
CONFIG_XILINX_MDM_0_MB_DBG_PORTS=1
CONFIG_XILINX_MDM_0_USE_UART=1
CONFIG_XILINX_MDM_0_UART_WIDTH=8
CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS=1
CONFIG_XILINX_MDM_0_INSTANCE="opb_mdm_0"
CONFIG_XILINX_MDM_0_HW_VER="2.01.a"
CONFIG_XILINX_MDM_0_IRQ=11
CONFIG_XILINX_UARTLITE_0_INSTANCE="console_uart"
CONFIG_XILINX_UARTLITE_0_BASEADDR=0xA0000000
CONFIG_XILINX_UARTLITE_0_HIGHADDR=0xA0001FFF
CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH=32
CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH=32
CONFIG_XILINX_UARTLITE_0_DATA_BITS=8
CONFIG_XILINX_UARTLITE_0_CLK_FREQ=100000000
CONFIG_XILINX_UARTLITE_0_BAUDRATE=115200
CONFIG_XILINX_UARTLITE_0_USE_PARITY=0
CONFIG_XILINX_UARTLITE_0_ODD_PARITY=0
CONFIG_XILINX_UARTLITE_0_INSTANCE="console_uart"
CONFIG_XILINX_UARTLITE_0_HW_VER="1.00.b"
CONFIG_XILINX_UARTLITE_0_IRQ=10
CONFIG_XILINX_INTC_0_INSTANCE="opb_intc_0"
CONFIG_XILINX_INTC_0_FAMILY="virtex4"
CONFIG_XILINX_INTC_0_Y=0
CONFIG_XILINX_INTC_0_X=0
CONFIG_XILINX_INTC_0_U_SET="intc"
CONFIG_XILINX_INTC_0_OPB_AWIDTH=32
CONFIG_XILINX_INTC_0_OPB_DWIDTH=32
CONFIG_XILINX_INTC_0_BASEADDR=0xD1000FC0
CONFIG_XILINX_INTC_0_HIGHADDR=0xD1000FDF
CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS=12
CONFIG_XILINX_INTC_0_KIND_OF_INTR=0x00000C00
CONFIG_XILINX_INTC_0_KIND_OF_EDGE=0x00000C00
CONFIG_XILINX_INTC_0_KIND_OF_LVL=0x000003FF
CONFIG_XILINX_INTC_0_HAS_IPR=1
CONFIG_XILINX_INTC_0_HAS_SIE=1
CONFIG_XILINX_INTC_0_HAS_CIE=1
CONFIG_XILINX_INTC_0_HAS_IVR=1
CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL=1
CONFIG_XILINX_INTC_0_IRQ_ACTIVE=1
CONFIG_XILINX_INTC_0_INSTANCE="opb_intc_0"
CONFIG_XILINX_INTC_0_HW_VER="1.00.c"
CONFIG_XILINX_TIMER_0_INSTANCE="opb_timer_0"
CONFIG_XILINX_TIMER_0_FAMILY="virtex4"
CONFIG_XILINX_TIMER_0_COUNT_WIDTH=32
CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY=0
CONFIG_XILINX_TIMER_0_TRIG0_ASSERT=1
CONFIG_XILINX_TIMER_0_TRIG1_ASSERT=1
CONFIG_XILINX_TIMER_0_GEN0_ASSERT=1
CONFIG_XILINX_TIMER_0_GEN1_ASSERT=1
CONFIG_XILINX_TIMER_0_OPB_AWIDTH=32
CONFIG_XILINX_TIMER_0_OPB_DWIDTH=32
CONFIG_XILINX_TIMER_0_BASEADDR=0xA2000000
CONFIG_XILINX_TIMER_0_HIGHADDR=0xA20000FF
CONFIG_XILINX_TIMER_0_INSTANCE="opb_timer_0"
CONFIG_XILINX_TIMER_0_HW_VER="1.00.b"
CONFIG_XILINX_TIMER_0_IRQ=0
CONFIG_XILINX_GPIO_0_INSTANCE="opb_gpio_0"
CONFIG_XILINX_GPIO_0_BASEADDR=0x90000000
CONFIG_XILINX_GPIO_0_HIGHADDR=0x900001FF
CONFIG_XILINX_GPIO_0_USER_ID_CODE=3
CONFIG_XILINX_GPIO_0_OPB_AWIDTH=32
CONFIG_XILINX_GPIO_0_OPB_DWIDTH=32
CONFIG_XILINX_GPIO_0_FAMILY="virtex4"
CONFIG_XILINX_GPIO_0_GPIO_WIDTH=27
CONFIG_XILINX_GPIO_0_ALL_INPUTS=0
CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT=0
CONFIG_XILINX_GPIO_0_IS_BIDIR=1
CONFIG_XILINX_GPIO_0_DOUT_DEFAULT=0x00000000
CONFIG_XILINX_GPIO_0_TRI_DEFAULT=0x04FFFE00
CONFIG_XILINX_GPIO_0_IS_DUAL=1
CONFIG_XILINX_GPIO_0_ALL_INPUTS_2=0
CONFIG_XILINX_GPIO_0_IS_BIDIR_2=0
CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2=0x00000000
CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2=0x00000003
CONFIG_XILINX_GPIO_0_INSTANCE="opb_gpio_0"
CONFIG_XILINX_GPIO_0_HW_VER="3.01.a"
CONFIG_XILINX_GPIO_1_INSTANCE="opb_gpio_exp_hdr_0"
CONFIG_XILINX_GPIO_1_BASEADDR=0x90001000
CONFIG_XILINX_GPIO_1_HIGHADDR=0x900011FF
CONFIG_XILINX_GPIO_1_USER_ID_CODE=3
CONFIG_XILINX_GPIO_1_OPB_AWIDTH=32
CONFIG_XILINX_GPIO_1_OPB_DWIDTH=32
CONFIG_XILINX_GPIO_1_FAMILY="virtex4"
CONFIG_XILINX_GPIO_1_GPIO_WIDTH=32
CONFIG_XILINX_GPIO_1_ALL_INPUTS=0
CONFIG_XILINX_GPIO_1_INTERRUPT_PRESENT=0
CONFIG_XILINX_GPIO_1_IS_BIDIR=1
CONFIG_XILINX_GPIO_1_DOUT_DEFAULT=0x00000000
CONFIG_XILINX_GPIO_1_TRI_DEFAULT=0xFFFFFFFF
CONFIG_XILINX_GPIO_1_IS_DUAL=1
CONFIG_XILINX_GPIO_1_ALL_INPUTS_2=0
CONFIG_XILINX_GPIO_1_IS_BIDIR_2=1
CONFIG_XILINX_GPIO_1_DOUT_DEFAULT_2=0x00000000
CONFIG_XILINX_GPIO_1_TRI_DEFAULT_2=0xFFFFFFFF
CONFIG_XILINX_GPIO_1_INSTANCE="opb_gpio_exp_hdr_0"
CONFIG_XILINX_GPIO_1_HW_VER="3.01.a"
CONFIG_XILINX_GPIO_2_INSTANCE="opb_gpio_char_lcd_0"
CONFIG_XILINX_GPIO_2_BASEADDR=0x90002000
CONFIG_XILINX_GPIO_2_HIGHADDR=0x900021FF
CONFIG_XILINX_GPIO_2_USER_ID_CODE=3
CONFIG_XILINX_GPIO_2_OPB_AWIDTH=32
CONFIG_XILINX_GPIO_2_OPB_DWIDTH=32
CONFIG_XILINX_GPIO_2_FAMILY="virtex4"
CONFIG_XILINX_GPIO_2_GPIO_WIDTH=7
CONFIG_XILINX_GPIO_2_ALL_INPUTS=0
CONFIG_XILINX_GPIO_2_INTERRUPT_PRESENT=0
CONFIG_XILINX_GPIO_2_IS_BIDIR=1
CONFIG_XILINX_GPIO_2_DOUT_DEFAULT=0x00000000
CONFIG_XILINX_GPIO_2_TRI_DEFAULT=0xFFFFFFFF
CONFIG_XILINX_GPIO_2_IS_DUAL=0
CONFIG_XILINX_GPIO_2_ALL_INPUTS_2=0
CONFIG_XILINX_GPIO_2_IS_BIDIR_2=1
CONFIG_XILINX_GPIO_2_DOUT_DEFAULT_2=0x00000000
CONFIG_XILINX_GPIO_2_TRI_DEFAULT_2=0xFFFFFFFF
CONFIG_XILINX_GPIO_2_INSTANCE="opb_gpio_char_lcd_0"
CONFIG_XILINX_GPIO_2_HW_VER="3.01.a"
CONFIG_XILINX_PS2_DUAL_REF_0_INSTANCE="opb_ps2_dual_ref_0"
CONFIG_XILINX_PS2_DUAL_REF_0_BASEADDR="0xA9000000"
CONFIG_XILINX_PS2_DUAL_REF_0_HIGHADDR="0xA9001FFF"
CONFIG_XILINX_PS2_DUAL_REF_0_INSTANCE="opb_ps2_dual_ref_0"
CONFIG_XILINX_PS2_DUAL_REF_0_HW_VER="1.00.a"
CONFIG_XILINX_PS2_DUAL_REF_0_SYS_INTR1_IRQ=9
CONFIG_XILINX_PS2_DUAL_REF_0_SYS_INTR2_IRQ=8
CONFIG_XILINX_IIC_0_INSTANCE="opb_iic_0"
CONFIG_XILINX_IIC_0_CLK_FREQ=100000000
CONFIG_XILINX_IIC_0_IIFREQ=100000
CONFIG_XILINX_IIC_0_TEN_BIT_ADR=0
CONFIG_XILINX_IIC_0_GPO_WIDTH=1
CONFIG_XILINX_IIC_0_DEV_BLK_ID=0
CONFIG_XILINX_IIC_0_DEV_MIR_ENABLE=0
CONFIG_XILINX_IIC_0_BASEADDR=0xA8000000
CONFIG_XILINX_IIC_0_HIGHADDR=0xA80001FF
CONFIG_XILINX_IIC_0_OPB_AWIDTH=32
CONFIG_XILINX_IIC_0_OPB_DWIDTH=32
CONFIG_XILINX_IIC_0_INSTANCE="opb_iic_0"
CONFIG_XILINX_IIC_0_HW_VER="1.01.c"
CONFIG_XILINX_IIC_0_IRQ=7
CONFIG_XILINX_AC97_CONTROLLER_REF_0_INSTANCE="opb_ac97_controller_ref_0"
CONFIG_XILINX_AC97_CONTROLLER_REF_0_BASEADDR=0xA6000000
CONFIG_XILINX_AC97_CONTROLLER_REF_0_HIGHADDR=0xA60000FF
CONFIG_XILINX_AC97_CONTROLLER_REF_0_OPB_DWIDTH=32
CONFIG_XILINX_AC97_CONTROLLER_REF_0_OPB_AWIDTH=32
CONFIG_XILINX_AC97_CONTROLLER_REF_0_PLAYBACK=1
CONFIG_XILINX_AC97_CONTROLLER_REF_0_RECORD=1
CONFIG_XILINX_AC97_CONTROLLER_REF_0_PLAY_INTR_LEVEL=2
CONFIG_XILINX_AC97_CONTROLLER_REF_0_REINTR_LEVEL=3
CONFIG_XILINX_AC97_CONTROLLER_REF_0_INSTANCE="opb_ac97_controller_ref_0"
CONFIG_XILINX_AC97_CONTROLLER_REF_0_HW_VER="1.00.a"
CONFIG_XILINX_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_IRQ=6
CONFIG_XILINX_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_IRQ=5
CONFIG_XILINX_V34_0_INSTANCE="plb_v34_0"
CONFIG_XILINX_V34_0_PLB_NUM_MASTERS=2
CONFIG_XILINX_V34_0_PLB_NUM_SLAVES=1
CONFIG_XILINX_V34_0_PLB_MID_WIDTH=1
CONFIG_XILINX_V34_0_PLB_AWIDTH=32
CONFIG_XILINX_V34_0_PLB_DWIDTH=64
CONFIG_XILINX_V34_0_DCR_INTFCE=1
CONFIG_XILINX_V34_0_BASEADDR=0x00000010
CONFIG_XILINX_V34_0_HIGHADDR=0x0000001F
CONFIG_XILINX_V34_0_DCR_AWIDTH=10
CONFIG_XILINX_V34_0_DCR_DWIDTH=32
CONFIG_XILINX_V34_0_EXT_RESET_HIGH=1
CONFIG_XILINX_V34_0_IRQ_ACTIVE=1
CONFIG_XILINX_V34_0_NUM_OPBCLK_PLB2OPB_REARB=100
CONFIG_XILINX_V34_0_INSTANCE="plb_v34_0"
CONFIG_XILINX_V34_0_HW_VER="1.02.a"
CONFIG_XILINX_DDR_0_INSTANCE="plb_ddr_0"
CONFIG_XILINX_DDR_0_INCLUDE_BURST_CACHELN_SUPPORT=1
CONFIG_XILINX_DDR_0_REG_DIMM=0
CONFIG_XILINX_DDR_0_NUM_BANKS_MEM=1
CONFIG_XILINX_DDR_0_NUM_CLK_PAIRS=1
CONFIG_XILINX_DDR_0_FAMILY="virtex4"
CONFIG_XILINX_DDR_0_INCLUDE_ECSUPPORT=0
CONFIG_XILINX_DDR_0_ENABLE_ECREG=0
CONFIG_XILINX_DDR_0_ECDEFAULT_ON=1
CONFIG_XILINX_DDR_0_INCLUDE_ECINTR=0
CONFIG_XILINX_DDR_0_INCLUDE_ECTEST=0
CONFIG_XILINX_DDR_0_ECSETHRESHOLD=1
CONFIG_XILINX_DDR_0_ECDETHRESHOLD=1
CONFIG_XILINX_DDR_0_ECPETHRESHOLD=1
CONFIG_XILINX_DDR_0_NUM_ECBITS=7
CONFIG_XILINX_DDR_0_DDR_TMRD=20000
CONFIG_XILINX_DDR_0_DDR_TWR=20000
CONFIG_XILINX_DDR_0_DDR_TWTR=1
CONFIG_XILINX_DDR_0_DDR_TRAS=60000
CONFIG_XILINX_DDR_0_DDR_TRC=90000
CONFIG_XILINX_DDR_0_DDR_TRFC=80000
CONFIG_XILINX_DDR_0_DDR_TRCD=30000
CONFIG_XILINX_DDR_0_DDR_TRRD=15000
CONFIG_XILINX_DDR_0_DDR_TREFC=70300000
CONFIG_XILINX_DDR_0_DDR_TREFI=7800000
CONFIG_XILINX_DDR_0_DDR_TRP=30000
CONFIG_XILINX_DDR_0_DDR_CAS_LAT=2
CONFIG_XILINX_DDR_0_DDR_DWIDTH=32
CONFIG_XILINX_DDR_0_DDR_AWIDTH=13
CONFIG_XILINX_DDR_0_DDR_COL_AWIDTH=9
CONFIG_XILINX_DDR_0_DDR_BANK_AWIDTH=2
CONFIG_XILINX_DDR_0_MEM0_BASEADDR=0x10000000
CONFIG_XILINX_DDR_0_MEM0_HIGHADDR=0x1FFFFFFF
CONFIG_XILINX_DDR_0_MEM1_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_DDR_0_MEM1_HIGHADDR=0x00000000
CONFIG_XILINX_DDR_0_MEM2_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_DDR_0_MEM2_HIGHADDR=0x00000000
CONFIG_XILINX_DDR_0_MEM3_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_DDR_0_MEM3_HIGHADDR=0x00000000
CONFIG_XILINX_DDR_0_ECBASEADDR=0x0F000000
CONFIG_XILINX_DDR_0_ECHIGHADDR=0x0F000FFF
CONFIG_XILINX_DDR_0_PLB_NUM_MASTERS=2
CONFIG_XILINX_DDR_0_PLB_MID_WIDTH=1
CONFIG_XILINX_DDR_0_PLB_AWIDTH=32
CONFIG_XILINX_DDR_0_PLB_DWIDTH=64
CONFIG_XILINX_DDR_0_PLB_CLK_PERIOD_PS=10000
CONFIG_XILINX_DDR_0_SIM_INIT_TIME_PS=200000000
CONFIG_XILINX_DDR_0_INSTANCE="plb_ddr_0"
CONFIG_XILINX_DDR_0_HW_VER="1.10.a"
CONFIG_XILINX_TFT_CNTLR_REF_0_INSTANCE="plb_tft_cntlr_ref_0"
CONFIG_XILINX_TFT_CNTLR_REF_0_DCR_BASEADDR="0b0010000000"
CONFIG_XILINX_TFT_CNTLR_REF_0_DCR_HIGHADDR="0b0010000001"
CONFIG_XILINX_TFT_CNTLR_REF_0_DEFAULT_TFT_BASE_ADDR="0b00010011111"
CONFIG_XILINX_TFT_CNTLR_REF_0_DPS_INIT="0b1"
CONFIG_XILINX_TFT_CNTLR_REF_0_ON_INIT="1"
CONFIG_XILINX_TFT_CNTLR_REF_0_INSTANCE="plb_tft_cntlr_ref_0"
CONFIG_XILINX_TFT_CNTLR_REF_0_HW_VER="1.00.b"
CONFIG_XILINX_ETHERNET_0_INSTANCE="opb_ethernet_0"
CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID=0
CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE=1
CONFIG_XILINX_ETHERNET_0_BASEADDR=0x60000000
CONFIG_XILINX_ETHERNET_0_HIGHADDR=0x60003FFF
CONFIG_XILINX_ETHERNET_0_RESET_PRESENT=1
CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER=1
CONFIG_XILINX_ETHERNET_0_DMA_PRESENT=1
CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE=1
CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH=32
CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH=32
CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS=10000
CONFIG_XILINX_ETHERNET_0_FAMILY="virtex4"
CONFIG_XILINX_ETHERNET_0_IPIF_FIFO_DEPTH=65536
CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD=0x0000001F
CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST=1
CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST=1
CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST=1
CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH=64
CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST=1
CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST=1
CONFIG_XILINX_ETHERNET_0_MII_EXIST=1
CONFIG_XILINX_ETHERNET_0_INSTANCE="opb_ethernet_0"
CONFIG_XILINX_ETHERNET_0_HW_VER="1.01.a"
CONFIG_XILINX_ETHERNET_0_IRQ=2
CONFIG_XILINX_EMC_0_INSTANCE="opb_emc_0"
CONFIG_XILINX_EMC_0_NUM_BANKS_MEM=2
CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS=0
CONFIG_XILINX_EMC_0_BASEADDR=0x24000000
CONFIG_XILINX_EMC_0_HIGHADDR=0x240001FF
CONFIG_XILINX_EMC_0_MEM0_BASEADDR=0x20000000
CONFIG_XILINX_EMC_0_MEM0_HIGHADDR=0x200FFFFF
CONFIG_XILINX_EMC_0_MEM1_BASEADDR=0x28000000
CONFIG_XILINX_EMC_0_MEM1_HIGHADDR=0x287FFFFF
CONFIG_XILINX_EMC_0_MEM2_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM2_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM3_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM3_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM4_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM4_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM5_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM5_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM6_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM6_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM7_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_0_MEM7_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_0_MEM0_WIDTH=32
CONFIG_XILINX_EMC_0_MEM1_WIDTH=32
CONFIG_XILINX_EMC_0_MEM2_WIDTH=32
CONFIG_XILINX_EMC_0_MEM3_WIDTH=32
CONFIG_XILINX_EMC_0_MEM4_WIDTH=32
CONFIG_XILINX_EMC_0_MEM5_WIDTH=32
CONFIG_XILINX_EMC_0_MEM6_WIDTH=32
CONFIG_XILINX_EMC_0_MEM7_WIDTH=32
CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH=32
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0=0
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1=0
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_4=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_5=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_6=1
CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_7=1
CONFIG_XILINX_EMC_0_SYNCH_MEM_0=1
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_0=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_0=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_0=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_0=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_0=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_0=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_0=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_1=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_1=110000
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_1=55000
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_1=70000
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_1=110000
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_1=55000
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_1=10000
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_1=35000
CONFIG_XILINX_EMC_0_SYNCH_MEM_2=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_2=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_2=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_2=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_2=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_3=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_3=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_3=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_3=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_3=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_4=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_4=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_4=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_4=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_4=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_4=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_5=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_5=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_5=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_5=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_5=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_5=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_6=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_6=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_6=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_6=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_6=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_6=0
CONFIG_XILINX_EMC_0_SYNCH_MEM_7=0
CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_7=2
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_SLOW_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_SLOW_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_MIN_PULSE_WIDTH_PS_7=0
CONFIG_XILINX_EMC_0_READ_ADDR_TO_OUT_FAST_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_ADDR_TO_OUT_FAST_PS_7=0
CONFIG_XILINX_EMC_0_READ_RECOVERY_BEFORE_WRITE_PS_7=0
CONFIG_XILINX_EMC_0_WRITE_RECOVERY_BEFORE_READ_PS_7=0
CONFIG_XILINX_EMC_0_OPB_DWIDTH=32
CONFIG_XILINX_EMC_0_OPB_AWIDTH=32
CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS=10000
CONFIG_XILINX_EMC_0_DEV_BLK_ID=1
CONFIG_XILINX_EMC_0_DEV_MIR_ENABLE=0
CONFIG_XILINX_EMC_0_INSTANCE="opb_emc_0"
CONFIG_XILINX_EMC_0_HW_VER="1.10.b"
CONFIG_XILINX_EMC_1_INSTANCE="opb_emc_usb_0"
CONFIG_XILINX_EMC_1_NUM_BANKS_MEM=1
CONFIG_XILINX_EMC_1_INCLUDE_NEGEDGE_IOREGS=0
CONFIG_XILINX_EMC_1_BASEADDR=0xA5100000
CONFIG_XILINX_EMC_1_HIGHADDR=0xA51001FF
CONFIG_XILINX_EMC_1_MEM0_BASEADDR=0xA5000000
CONFIG_XILINX_EMC_1_MEM0_HIGHADDR=0xA50000FF
CONFIG_XILINX_EMC_1_MEM1_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM1_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM2_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM2_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM3_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM3_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM4_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM4_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM5_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM5_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM6_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM6_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM7_BASEADDR=0xFFFFFFFF
CONFIG_XILINX_EMC_1_MEM7_HIGHADDR=0x00000000
CONFIG_XILINX_EMC_1_MEM0_WIDTH=32
CONFIG_XILINX_EMC_1_MEM1_WIDTH=32
CONFIG_XILINX_EMC_1_MEM2_WIDTH=32
CONFIG_XILINX_EMC_1_MEM3_WIDTH=32
CONFIG_XILINX_EMC_1_MEM4_WIDTH=32
CONFIG_XILINX_EMC_1_MEM5_WIDTH=32
CONFIG_XILINX_EMC_1_MEM6_WIDTH=32
CONFIG_XILINX_EMC_1_MEM7_WIDTH=32
CONFIG_XILINX_EMC_1_MAX_MEM_WIDTH=32
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_0=0
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_1=1
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_2=1
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_3=1
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_4=1
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_5=1
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_6=1
CONFIG_XILINX_EMC_1_INCLUDE_DATAWIDTH_MATCHING_7=1
CONFIG_XILINX_EMC_1_SYNCH_MEM_0=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_0=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_0=21000
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_0=42000
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_0=24000
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_0=210000
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_0=42000
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_0=84000
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_0=84000
CONFIG_XILINX_EMC_1_SYNCH_MEM_1=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_1=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_1=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_1=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_1=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_1=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_1=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_1=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_1=0
CONFIG_XILINX_EMC_1_SYNCH_MEM_2=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_2=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_2=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_2=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_2=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_2=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_2=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_2=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_2=0
CONFIG_XILINX_EMC_1_SYNCH_MEM_3=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_3=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_3=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_3=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_3=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_3=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_3=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_3=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_3=0
CONFIG_XILINX_EMC_1_SYNCH_MEM_4=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_4=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_4=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_4=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_4=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_4=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_4=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_4=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_4=0
CONFIG_XILINX_EMC_1_SYNCH_MEM_5=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_5=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_5=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_5=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_5=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_5=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_5=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_5=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_5=0
CONFIG_XILINX_EMC_1_SYNCH_MEM_6=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_6=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_6=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_6=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_6=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_6=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_6=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_6=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_6=0
CONFIG_XILINX_EMC_1_SYNCH_MEM_7=0
CONFIG_XILINX_EMC_1_SYNCH_PIPEDELAY_7=2
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_SLOW_PS_7=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_SLOW_PS_7=0
CONFIG_XILINX_EMC_1_WRITE_MIN_PULSE_WIDTH_PS_7=0
CONFIG_XILINX_EMC_1_READ_ADDR_TO_OUT_FAST_PS_7=0
CONFIG_XILINX_EMC_1_WRITE_ADDR_TO_OUT_FAST_PS_7=0
CONFIG_XILINX_EMC_1_READ_RECOVERY_BEFORE_WRITE_PS_7=0
CONFIG_XILINX_EMC_1_WRITE_RECOVERY_BEFORE_READ_PS_7=0
CONFIG_XILINX_EMC_1_OPB_DWIDTH=32
CONFIG_XILINX_EMC_1_OPB_AWIDTH=32
CONFIG_XILINX_EMC_1_OPB_CLK_PERIOD_PS=10000
CONFIG_XILINX_EMC_1_DEV_BLK_ID=1
CONFIG_XILINX_EMC_1_DEV_MIR_ENABLE=0
CONFIG_XILINX_EMC_1_INSTANCE="opb_emc_usb_0"
CONFIG_XILINX_EMC_1_HW_VER="1.10.b"
CONFIG_XILINX_SYSACE_0_INSTANCE="opb_sysace_0"
CONFIG_XILINX_SYSACE_0_BASEADDR=0xCF000000
CONFIG_XILINX_SYSACE_0_HIGHADDR=0xCF0001FF
CONFIG_XILINX_SYSACE_0_MEM_WIDTH=16
CONFIG_XILINX_SYSACE_0_OPB_DWIDTH=32
CONFIG_XILINX_SYSACE_0_OPB_AWIDTH=32
CONFIG_XILINX_SYSACE_0_INSTANCE="opb_sysace_0"
CONFIG_XILINX_SYSACE_0_HW_VER="1.00.b"
CONFIG_XILINX_SYSACE_0_IRQ=4
CONFIG_XILINX_SYSACE_NUM_INSTANCES=1
CONFIG_XILINX_TIMER_NUM_INSTANCES=1
CONFIG_XILINX_UARTLITE_NUM_INSTANCES=1
CONFIG_XILINX_AC97_CONTROLLER_REF_NUM_INSTANCES=1
CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES=2
CONFIG_XILINX_TFT_CNTLR_REF_NUM_INSTANCES=1
CONFIG_XILINX_V34_NUM_INSTANCES=1
CONFIG_XILINX_INTC_NUM_INSTANCES=1
CONFIG_XILINX_DDR_NUM_INSTANCES=1
CONFIG_XILINX_EMC_NUM_INSTANCES=2
CONFIG_XILINX_IIC_NUM_INSTANCES=1
CONFIG_XILINX_MDM_NUM_INSTANCES=1
CONFIG_XILINX_PS2_DUAL_REF_NUM_INSTANCES=1
CONFIG_XILINX_ETHERNET_NUM_INSTANCES=1
CONFIG_XILINX_GPIO_NUM_INSTANCES=3
CONFIG_XILINX_ENET=y
CONFIG_MBVANILLA_CMDLINE=y
CONFIG_ZERO_BSS=y
CONFIG_MICROBLAZE_DEBUGGING=y

CONFIG_NET=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_FLAT=y
CONFIG_BINFMT_ZFLAT=y

CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_RAM=y

CONFIG_MTD_UCLINUX=y




CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096

CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y


















CONFIG_RAMFS=y
CONFIG_PROC_FS=y
CONFIG_ROMFS_FS=y
CONFIG_EXT2_FS=y

CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_SUNRPC=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y





CONFIG_FULLDEBUG=y


CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y


CONFIG_USER_INIT_INIT=y
CONFIG_USER_SH_SH=y
CONFIG_USER_VERSION_VERSION=y
CONFIG_USER_LOGIN_LOGIN=y
CONFIG_USER_AGETTY_AGETTY=y
CONFIG_USER_LOGIN_PASSWD=y

CONFIG_LIB_ZLIB_FORCE=y

CONFIG_USER_NETFLASH_NETFLASH=y
CONFIG_USER_NETFLASH_WITH_FTP=y
CONFIG_USER_NETFLASH_VERSION=y
CONFIG_USER_NETFLASH_VERSION_ALLOW_CURRENT=y
CONFIG_USER_NETFLASH_VERSION_ALLOW_OLDER=y
CONFIG_USER_MTDUTILS=y
CONFIG_USER_MTDUTILS_ERASE=y
CONFIG_USER_MTDUTILS_ERASEALL=y
CONFIG_LIB_ZLIB=y

CONFIG_USER_FLATFSD_FLATFSD=y
CONFIG_USER_FLATFSD_AUTO=y

CONFIG_USER_DHCPCD_NEW_DHCPCD=y
CONFIG_USER_FTPD_FTPD=y
CONFIG_USER_ROUTE_IFCONFIG=y
CONFIG_USER_INETD_INETD=y
CONFIG_USER_PING_PING=y
CONFIG_USER_TCPDUMP_TCPDUMP=y
CONFIG_LIB_LIBPCAP=y
CONFIG_USER_TELNETD_TELNETD=y
CONFIG_USER_TELNETD_DOES_NOT_USE_OPENPTY=y
CONFIG_USER_THTTPD_THTTPD=y
CONFIG_USER_NET_TOOLS_HOSTNAME=y

CONFIG_USER_HD_HD=y
CONFIG_USER_FILEUTILS_CAT=y
CONFIG_USER_FILEUTILS_CHMOD=y
CONFIG_USER_FILEUTILS_CMP=y
CONFIG_USER_FILEUTILS_CP=y
CONFIG_USER_FILEUTILS_LN=y
CONFIG_USER_FILEUTILS_MKDIR=y
CONFIG_USER_FILEUTILS_MV=y
CONFIG_USER_FILEUTILS_RM=y
CONFIG_USER_FILEUTILS_TOUCH=y
CONFIG_USER_SHUTILS_BASENAME=y
CONFIG_USER_SHUTILS_DATE=y
CONFIG_USER_SHUTILS_ECHO=y
CONFIG_USER_SHUTILS_FALSE=y
CONFIG_USER_SHUTILS_PWD=y
CONFIG_USER_SHUTILS_TRUE=y
CONFIG_USER_SHUTILS_UNAME=y
CONFIG_USER_SYSUTILS_REBOOT=y
CONFIG_USER_SYSUTILS_SHUTDOWN=y
CONFIG_USER_SYSUTILS_FREE=y
CONFIG_USER_SYSUTILS_HOSTNAME=y
CONFIG_USER_SYSUTILS_KILL=y
CONFIG_USER_SYSUTILS_PS=y

CONFIG_USER_BUSYBOX_BUSYBOX=y
CONFIG_USER_BUSYBOX_DD=y
CONFIG_USER_BUSYBOX_INSMOD=y
CONFIG_USER_BUSYBOX_LSMOD=y
CONFIG_USER_BUSYBOX_MODPROBE=y
CONFIG_USER_BUSYBOX_RMMOD=y
CONFIG_USER_BUSYBOX_2_4_MODULES=y
CONFIG_USER_BUSYBOX_INSMOD_KSYMOOPS_SYMBOLS=y
CONFIG_USER_BUSYBOX_KILL=y
CONFIG_USER_BUSYBOX_KILLALL=y
CONFIG_USER_BUSYBOX_LOGIN=y
CONFIG_USER_BUSYBOX_LS=y
CONFIG_USER_BUSYBOX_LS_USERNAME=y
CONFIG_USER_BUSYBOX_LS_TIMESTAMPS=y
CONFIG_USER_BUSYBOX_LS_FILETYPES=y
CONFIG_USER_BUSYBOX_LS_SORTFILES=y
CONFIG_USER_BUSYBOX_LS_RECURSIVE=y
CONFIG_USER_BUSYBOX_LS_FOLLOWLINKS=y
CONFIG_USER_BUSYBOX_MOUNT=y
CONFIG_USER_BUSYBOX_MOUNT_LOOP=y
CONFIG_USER_BUSYBOX_NFSMOUNT=y
CONFIG_USER_BUSYBOX_TEST=y
CONFIG_USER_BUSYBOX_TFTP=y
CONFIG_USER_BUSYBOX_TFTP_PUT=y
CONFIG_USER_BUSYBOX_TFTP_GET=y
CONFIG_USER_BUSYBOX_TRUE_FALSE=y
CONFIG_USER_BUSYBOX_UPTIME=y
CONFIG_USER_BUSYBOX_VI=y
CONFIG_USER_BUSYBOX_VI_COLON=y
CONFIG_USER_BUSYBOX_VI_YANKMARK=y
CONFIG_USER_BUSYBOX_VI_SEARCH=y
CONFIG_USER_BUSYBOX_VI_READONLY=y
CONFIG_USER_BUSYBOX_VI_SETOPTS=y
CONFIG_USER_BUSYBOX_VI_SET=y
CONFIG_USER_BUSYBOX_VI_WIN_RESIZE=y
CONFIG_USER_BUSYBOX_WGET=y
CONFIG_USER_BUSYBOX_WGET_STATUSBAR=y
CONFIG_USER_BUSYBOX_VERBOSE_USAGE=y
CONFIG_USER_BUSYBOX_AUTOWIDTH=y
CONFIG_USER_BUSYBOX_HUMAN_READABLE=y




CONFIG_USER_RAMIMAGE_NONE=y

References:
- Re: [microblaze-uclinux] ML401 update
  - From: Greg Miller

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