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[microblaze-uclinux] FSL question

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] FSL question
From: "Taeweon Suh" <suhtw@xxxxxxxxxxxxxx>
Date: Sun, 27 Feb 2005 20:51:36 -0500 (EST)
Importance: Normal
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
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Hi everyone,

I am using Avnet Virtex-II Pro development board with EDK 6.3 and
successfully (i think, actually i have some questions to ask later)
downloaded image.bin and saw booting messages, and logged on with "root".

But, the download speed is too slow (15+ min), so I am trying to use the fsl.
After referencing the Xilinx manual and John's reference design, I made my
hardware platform and downloaded the image.bin.
It only took 2 seconds to download 2MB image file.
But, after downloading, the commands doesn't work.

The following is the steps I took.

Microblaze Processor 1 Configuration :
--------------------------------------
Version------------------------------3.00.a
No of PC Breakpoints-----------------2
No of Read Addr/Data Watchpoints-----1
No of Write Addr/Data Watchpoints----1
Instruction Cache Support-------------off
Data Cache Support--------------------off
MBsfsl<0>-MDMmfsl<0> Connected--------Yes
JTAG MDM Connected to Microblaze 1
Connected to "mb" target. id = 0
Starting GDB server for "mb" target <id=0> at TCP port no 1234
XMD% rrd

shows all registers having all "0"

XMD% dow -data image.bin 0x86000000 (it took only 1-2 seconds)
XMD% rrd
  Operation Not Supported
XMD% rwr 32 0x86000000
  Operation Not Supported


So, I am not even sure if the download was done correctly or not because
all commands doesn't work after the download

The following are MHS and MSS files.
Thanks in advance for any comments!

#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.12.3
# Fri Feb 04 11:19:06 2005
# Target Board:  Avnet Avnet Virtex-II Pro Development Board (VP20) Rev 1.0
# Family:	 virtex2p
# Device:	 XC2VP20
# Package:	 FF896
# Speed Grade:	 -5
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :   8 KB
# Total Off Chip Memory :  32 MB
# - SDRAM_64Mx16 =  32 MB
#
##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = IN
 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_DQ_pin = fpga_0_SDRAM_64Mx16_SDRAM_DQ, VEC
= [0:31], DIR = INOUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_BankAddr_pin =
fpga_0_SDRAM_64Mx16_SDRAM_BankAddr, VEC = [0:1], DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_Addr_pin = fpga_0_SDRAM_64Mx16_SDRAM_Addr,
VEC = [0:11], DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_DQM_pin = fpga_0_SDRAM_64Mx16_SDRAM_DQM,
VEC = [0:3], DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_CASn_pin = fpga_0_SDRAM_64Mx16_SDRAM_CASn,
DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_RASn_pin = fpga_0_SDRAM_64Mx16_SDRAM_RASn,
DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_Clk_pin = fpga_0_SDRAM_64Mx16_SDRAM_Clk,
DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_WEn_pin = fpga_0_SDRAM_64Mx16_SDRAM_WEn,
DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_SDRAM_CSn_pin = fpga_0_SDRAM_64Mx16_SDRAM_CSn,
DIR = OUT
 PORT fpga_0_SDRAM_64Mx16_emc_disable_flash_pin = net_vcc, DIR = OUTPUT
 PORT fpga_0_SDRAM_64Mx16_emc_disable_sram_pin = net_vcc, DIR = OUTPUT
 PORT fpga_0_SDRAM_64Mx16_emc_disable_buffer_pin = net_vcc, DIR = OUTPUT
 PORT fpga_0_SDRAM_64Mx16_emc_disable_sysace_pin = net_vcc, DIR = OUT
 PORT fpga_0_Ethernet_MAC_DUMMY_ETH_TXER_pin = net_gnd, DIR = OUT
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk,
DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk,
DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin =
fpga_0_Ethernet_MAC_PHY_rx_data, VEC = [3:0], DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er,
DIR = IN
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en,
DIR = OUT
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin =
fpga_0_Ethernet_MAC_PHY_tx_data, VEC = [3:0], DIR = OUT
 PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin =
fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = INOUT
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n,
DIR = OUT
 PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin =
fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = INOUT
 PORT sys_clk_pin = sys_clk_s, DIR = IN, SIGIS = CLK
 PORT sys_rst_pin = sys_rst_s, DIR = IN


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_DIV = 1
 PARAMETER C_USE_MSR_INSTR = 1
 PARAMETER C_FSL_LINKS = 1
 BUS_INTERFACE SFSL0 = download_link_fsl_v20
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
# PORT DBG_REG_EN = DBG_REG_EN_s
# PORT DBG_CAPTURE = DBG_CAPTURE_s
# PORT DBG_TDI = DBG_TDI_s
# PORT DBG_CLK = DBG_CLK_s
# PORT DBG_TDO = DBG_TDO_s
 PORT Interrupt = Interrupt
# PORT DBG_UPDATE = DBG_UPDATE_s
 PORT CLK = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT OPB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84020000
 PARAMETER C_HIGHADDR = 0x8402ffff
 PARAMETER C_WRITE_FSL_PORTS = 1
 BUS_INTERFACE MFSL0 = download_link_fsl_v20
 BUS_INTERFACE SOPB = mb_opb
# PORT DBG_TDI_0 = DBG_TDI_s
# PORT DBG_CLK_0 = DBG_CLK_s
 PORT OPB_Clk = sys_clk_s
# PORT DBG_REG_EN_0 = DBG_REG_EN_s
# PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
# PORT DBG_UPDATE_0 = DBG_UPDATE_s
# PORT DBG_TDO_0 = DBG_TDO_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_rst_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x84030000
 PARAMETER C_HIGHADDR = 0x8403ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT TX = fpga_0_RS232_TX
 PORT Interrupt = RS232_Interrupt
 PORT RX = fpga_0_RS232_RX
END

BEGIN opb_sdram
 PARAMETER INSTANCE = SDRAM_64Mx16
 PARAMETER HW_VER = 1.00.e
 PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_SDRAM_TMRD = 2
 PARAMETER C_SDRAM_TCCD = 1
 PARAMETER C_SDRAM_TRAS = 50000
 PARAMETER C_SDRAM_TRC = 100000
 PARAMETER C_SDRAM_TRFC = 100000
 PARAMETER C_SDRAM_TRCD = 20000
 PARAMETER C_SDRAM_TRRD = 20000
 PARAMETER C_SDRAM_TRP = 20000
 PARAMETER C_SDRAM_TREF = 64
 PARAMETER C_SDRAM_CAS_LAT = 2
 PARAMETER C_SDRAM_COL_AWIDTH = 9
 PARAMETER C_SDRAM_BANK_AWIDTH = 2
 PARAMETER C_SDRAM_AWIDTH = 12
 PARAMETER C_SDRAM_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x86000000
 PARAMETER C_HIGHADDR = 0x87ffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT SDRAM_Addr = fpga_0_SDRAM_64Mx16_SDRAM_Addr
 PORT SDRAM_BankAddr = fpga_0_SDRAM_64Mx16_SDRAM_BankAddr
 PORT OPB_Clk = sys_clk_s
 PORT SDRAM_CLK_in = sys_clk_s
 PORT SDRAM_WEn = fpga_0_SDRAM_64Mx16_SDRAM_WEn
 PORT SDRAM_RASn = fpga_0_SDRAM_64Mx16_SDRAM_RASn
 PORT SDRAM_DQM = fpga_0_SDRAM_64Mx16_SDRAM_DQM
 PORT SDRAM_DQ = fpga_0_SDRAM_64Mx16_SDRAM_DQ
 PORT SDRAM_Clk = fpga_0_SDRAM_64Mx16_SDRAM_Clk
 PORT SDRAM_CSn = fpga_0_SDRAM_64Mx16_SDRAM_CSn
 PORT SDRAM_CASn = fpga_0_SDRAM_64Mx16_SDRAM_CASn
END

BEGIN opb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DMA_PRESENT = 1
 PARAMETER C_BASEADDR = 0x84040000
 PARAMETER C_HIGHADDR = 0x8404ffff
 PARAMETER C_IPIF_FIFO_DEPTH = 65536
 PARAMETER C_DEV_BLK_ID = 0
 BUS_INTERFACE SOPB = mb_opb
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = opb_timer_1_Interrupt
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x84010000
 PARAMETER C_HIGHADDR = 0x8401ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT Intr = Ethernet_MAC_IP2INTC_Irpt & opb_uartlite_dummy_Intr &
RS232_Interrupt & opb_timer_1_Interrupt
 PORT Irq = Interrupt
END

BEGIN opb_gpio
 PARAMETER INSTANCE = opb_gpio_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_GPIO_WIDTH = 24
 PARAMETER C_BASEADDR = 0x840E0000
 PARAMETER C_HIGHADDR = 0x840e00ff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = opb_uartlite_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_BASEADDR = 0x85000000
 PARAMETER C_HIGHADDR = 0x8500ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT Interrupt = opb_uartlite_dummy_Intr
 PORT RX = net_gnd
 PORT TX = opb_uartlite_0_TX
END

BEGIN fsl_v20
 PARAMETER INSTANCE = download_link_fsl_v20
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT FSL_Clk = sys_rst_s
 PORT SYS_Rst = sys_rst_s
END



-------------------------------------------


 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER main_memory = SDRAM_64Mx16
# PARAMETER flash_memory = none
 PARAMETER lmb_memory = ilmb_cntlr
 PARAMETER stdout = RS232
 PARAMETER stdin = RS232
END


# PARAMETER flash_memory = none
BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = RS232
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = sdram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = SDRAM_64Mx16
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = emac
 PARAMETER DRIVER_VER = 1.00.f
 PARAMETER HW_INSTANCE = Ethernet_MAC
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_timer_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = intc
 PARAMETER DRIVER_VER = 1.00.c
 PARAMETER HW_INSTANCE = opb_intc_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = opb_gpio_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_uartlite_0
END








----------------------------------------------
Taeweon Suh

Ph.D. Candidate
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia USA

Lab: CoC345
Tel: +1-404-385-6273
E-mail: suhtw@ece.gatech.edu
----------------------------------------------

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