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Re: [microblaze-uclinux] FSL question

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] FSL question
From: Raj Nagarajan <raj.nagarajan@xxxxxxxxxx>
Date: Sun, 27 Feb 2005 22:18:43 -0800
In-reply-to: <1365.130.207.231.23.1109555496.squirrel@130.207.231.23>
Organization: Xilinx Inc.
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> 
> BEGIN fsl_v20
>  PARAMETER INSTANCE = download_link_fsl_v20
>  PARAMETER HW_VER = 2.00.a
>  PARAMETER C_EXT_RESET_HIGH = 0
>  PORT FSL_Clk = sys_rst_s
>  PORT SYS_Rst = sys_rst_s
> END
> 
> 
> 

Your FSL clock is connected to Reset.. Connect it to sys_clk_s..

- Raj

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