[microblaze-uclinux] Ethernet update for David Banas' NuHorizons board project

[Mike <leem1@xxxxxxxxxx>]

>Mike,
>
>How'd you get the design to meet timing closure at 67 MHz? When I 
>look at my timing report for a 50 MHz clock, it shows that I just barely made it!
>
>David Banas


David,
  I am off today, and I just joined the list from home so I could
mention a different problem.

  As far as the timing goes, I do not recall doing anything special.
It seems like some timings are not proportional to the bus speed.
They are right at the edge no matter how fast or slow you go.
 Other possibilities:  3S2000 vs. 3S1500 - easier routing?
 Maybe I set a global 'try harder' variable somewhere?
  Sadly, I do not have enough Xilinx HW/SW at home.

  The other problem seems to be OS timing, at least.  
After the speed change, my reported Dhrystones went down
slightly.  14xxx to 13xxx.  I think that it is really faster, but the
OS does not know that the period of the system timer has
changed.

 The "at least" part is that later, I could not detect the flash 
anymore.   I am not sure if this was a real problem, or if I 
grabbed the wrong file somewhere, while making a minor
change to something or other.

Michael Lee





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