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RE: [microblaze-uclinux] Ethernet update for David Banas' NuHorizons board project

Mike,

Can you post the timing constraint report portion of your par report,
please? You'll find it near the bottom of your "xflow.log" file (in the
"Reference Files -> Log Files" branch of the "System" tab), just above the
actual timing analyzer's report. Here's mine, for reference:

--------- timing portion of par report begins here. ------------
Timing Score: 27647

WARNING:Par:62 - Timing constraints have not been met.

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------
----
  Constraint                                | Requested  | Actual     |
Logic
                                            |            |            |
Levels
----------------------------------------------------------------------------
----
  NET "enet_rx_clk_IBUF" MAXSKEW = 2 nS     | 2.000ns    | 1.243ns    | N/A

----------------------------------------------------------------------------
----
  NET "enet_rx_clk_IBUF" PERIOD =  40 nS    | 40.000ns   | 17.922ns   | 1

  HIGH 14 nS                                |            |            |

----------------------------------------------------------------------------
----
  NET "enet_tx_clk_IBUF" MAXSKEW = 2 nS     | 2.000ns    | 1.302ns    | N/A

----------------------------------------------------------------------------
----
  NET "enet_tx_clk_IBUF" PERIOD =  40 nS    | 40.000ns   | 9.564ns    | 1

  HIGH 14 nS                                |            |            |

----------------------------------------------------------------------------
----
  TSTXOUT_ethernet = MAXDELAY FROM TIMEGRP  | 10.000ns   | 5.138ns    | 0

  "TXCLK_GRP_ethernet" TO TIMEGRP "PADS" 10 |            |            |

   nS                                       |            |            |

----------------------------------------------------------------------------
----
  TSRXIN_ethernet = MAXDELAY FROM TIMEGRP " | 6.000ns    | 4.653ns    | 1

  PADS" TO TIMEGRP "RXCLK_GRP_ethernet" 6 n |            |            |

  S                                         |            |            |

----------------------------------------------------------------------------
----
  TS_ext_clk = PERIOD TIMEGRP "ext_clk"  20 | N/A        | N/A        | N/A

   nS   HIGH 50.000000 %                    |            |            |

----------------------------------------------------------------------------
----
* TS_system_dcm_system_dcm_CLKFX_BUF = PERI | 15.000ns   | 17.362ns   | 11

  OD TIMEGRP "system_dcm_system_dcm_CLKFX_B |            |            |

  UF" TS_ext_clk / 1.333333  HIGH 50.000 %  |            |            |

----------------------------------------------------------------------------
----


1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
--------- timing portion of par report ends here. ------------

As you can see, I missed by over 2ns! I must be doing something terribly
wrong, and I'd like to figure out what it is, pronto.

Thanks,

David Banas
Field Applications Engineer
Nu Horizons Electronics Corp.
2070 Ringwood Avenue
San Jose, CA 95131
(408)434-0800 - office
(415)846-5837 - cell
http://www.nuhorizons.com

> -----Original Message-----
> From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-
> uclinux@itee.uq.edu.au] On Behalf Of Mike
> Sent: Friday, March 25, 2005 6:48 AM
> To: microblaze-uclinux@itee.uq.edu.au
> Subject: [microblaze-uclinux] Ethernet update for David Banas' NuHorizons
> board project
>
> >Mike,
> >
> >How'd you get the design to meet timing closure at 67 MHz? When I
> >look at my timing report for a 50 MHz clock, it shows that I just barely
> made it!
> >
> >David Banas
>
>
> David,
>   I am off today, and I just joined the list from home so I could
> mention a different problem.
>
>   As far as the timing goes, I do not recall doing anything special.
> It seems like some timings are not proportional to the bus speed.
> They are right at the edge no matter how fast or slow you go.
>  Other possibilities:  3S2000 vs. 3S1500 - easier routing?
>  Maybe I set a global 'try harder' variable somewhere?
>   Sadly, I do not have enough Xilinx HW/SW at home.
>
>   The other problem seems to be OS timing, at least.
> After the speed change, my reported Dhrystones went down
> slightly.  14xxx to 13xxx.  I think that it is really faster, but the
> OS does not know that the period of the system timer has
> changed.
>
>  The "at least" part is that later, I could not detect the flash
> anymore.   I am not sure if this was a real problem, or if I
> grabbed the wrong file somewhere, while making a minor
> change to something or other.
>
> Michael Lee
>
>
>
>
>
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