RE: [microblaze-uclinux] auto-config question

["wlovell" <wlovell@xxxxxxxxxxxxxxxxx>]

John;
Thank you for the response. I'll go see why the MSS is the way it is. I let
the system autogenerate it, looks like that is not a good idea.

The programmer had a question on the Xilinx Ethernetlite IP, in that he was
looking for drivers do you know of any for the uClinux?

Thanks again.

William Lovell, Senior Design Engineer

PSoC & Xilinx Consultant

c-Link Systems, Inc.

PO Box 295

Waterford, ME 04088

P - 207-583-6470

F - 207-583-6247

wlovell@c-linksystems.com <mailto:wlovell@c-linksystems.com>

www.c-linksystems.com <http://www.c-linksystems.com>



-----Original Message-----
From: John Williams [mailto:jwilliams@itee.uq.edu.au]
Sent: Saturday, April 23, 2005 22:13 PM
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] auto-config question


Hi William,

wlovell wrote:

> I am handing the config file. It appears that the auto-config generator
> looks at the EMC says ok 4 banks and the largest is 0x00000000 -
> 0xFFFFFFFF (default value from the IP I presume) I only have one bank on
> each of the EMC IPs. The programmer can not get the kernel built with
> the file, I presume from his complaints because his system looks at all
> the different addresses and sees all sorts of over laps.

 From your auto-config.in:

# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0xffffffff
define_hex CONFIG_XILINX_ERAM_SIZE 0x00000002

# FLASH_MEMORY Settings
define_hex CONFIG_XILINX_FLASH_START 0xffffffff
define_hex CONFIG_XILINX_FLASH_SIZE 0x00000002

The MAIN_MEMORY and FLASH_MEMORY settings in your MSS file are wrong,
you are missing the _BANK=... option.  This is necessary to specify
which specific bank of the memory controller instance controls the memory.

It should probably look something ilke this:

BEGIN OS
...

   PARAMETER MAIN_MEMORY=sram
   PARAMETER MAIN_MEMORY_BANK=0
   PARAMETER FLASH_MEMORY=flash
   PARAMETER FLASH_MEMORY_BANK=0
...
END

Also you have other wierdness in your MHS file:

define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x00000FFF
...
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x00001000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x00001FFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1

Your cacheable address ranges overlap with the LMB memory space.  While
not strictly wrong, this is just a waste of BRAM.  Caching LMB memory
has no effect, you'll be much better to cache the cacheable address
range to match the SRAM region.

Regards,

John

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