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[microblaze-uclinux] Port to new card and microblaze not starting
Hello,
I am working on porting Microblaze uclinux to a new board : here are the
characteristics :
Virtex-II 1000
1 Mb SRAM
32 Mb SDRAM
1 serial port
Some leds and switchs (gpio)
As you can see, this is rather simple hardware, but some extension bords
(whith namely FLASH and bluetooth chips) are to come. But anyway, I'm
trying to use the uclinux-auto as a basis for the port. Until here what
I have done is to remove the things I didn't need (DDR Controller -
replaced by SDRAM Controller, own SRAM memory controller, remove
Ethernet). All the new things (SDRAM controller and SRAM) work with a
standalone Microblaze.
Now my problem is that I cannot make the uclinux Microblaze even boot
(cannot see the bootloader start, or cannot access it through xmd : here
is what I get with XMD :
> XMD%
> Loading XMP File..
> Loading MHS File..
> Processor(s) in System ::
>
> Microblaze(1) : microblaze_0
> Address Map for Processor microblaze_0
> (0x00000000-0x00003fff) dlmb_cntlr dlmb
> (0x00000000-0x00003fff) ilmb_cntlr ilmb
> (0x80000000-0x81ffffff) sdram_controller mb_opb
> (0xffe00000-0xffefffff) sram_flash mb_opb
> (0xffff0000-0xffff01ff) sram_flash mb_opb
> (0xffff1000-0xffff10ff) system_timer mb_opb
> (0xffff2000-0xffff20ff) console_uart mb_opb
> (0xffff3000-0xffff30ff) system_intc mb_opb
> (0xffff5000-0xffff50ff) system_gpio mb_opb
> (0xffffc000-0xffffc0ff) debug_module mb_opb
>
> Loading MSS File..
> Executing Connect Cmd: connect mb mdm -cable type xilinx_parallel port LPT1
> -debugdevice cpunr 1 -pfsl port 0 type s
> Connecting to cable (Parallel Port - LPT1).
> Checking cable driver.
> Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h.
> ECP base address = 0778h.
> ECP hardware is detected.
> Cable connection established.
> Connecting to cable (Parallel Port - LPT1) in ECP mode.
> Checking cable driver.
> Driver xpc4drvr.sys version = 1.0.3.0. LPT base address = 0378h.
> Cable Type = 1, Revision = 3.
> Cable connection established.
>
> JTAG chain configuration
> --------------------------------------------------
> Device ID Code IR Length Part Name
> 1 01028093 6 XC2V1000
> Assuming, Device No: 1 contains the MicroBlaze system
> Connected to the JTAG MicroBlaze Debug Module (MDM)
> No of processors = 1
>
> MicroBlaze Processor 1 Configuration :
> -------------------------------------
> Version............................3.00.a
> No of PC Breakpoints...............2
> No of Read Addr/Data Watchpoints...1
> No of Write Addr/Data Watchpoints..1
> Instruction Cache Support..........on
> Instruction Cache Base Address.....0x80000000
> Instruction Cache High Address.....0x81ffffff
> Data Cache Support.................on
> Data Cache Base Address............0x80000000
> Data Cache High Address............0x81ffffff
> MBsfsl(0)-MDMmfsl(0) Connected..........Yes
> Closing MDM communication with Processor 1
>
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to Stop MicroBlaze
> Verify if FPGA is configured and MicroBlaze System Clock is connected properly
> Unable to connect to MicroBlaze
I may have some problems with the system clocks since I have been
changing things from the original design ones. So I attach my actual
project files to the message so that you can maybe check my clocks or
whatever.
What I have done with the clocks is that my system only has an external
25 Mhz clock which I directly use as the system clock (it's how I used
it in my standalone design and it was working)
Thx in advance
Valentin Longchamp
# ##############################################################################
# Target Board: Memec Design Virtex-2 1000 Development Board
# with P160 Comm Module
# Family: virtex2
# Device: XCV21000
# Package:
# Speed Grade: -6
# Processor: Microblaze
# Debug interface: On-Chip HW Debug Module
# On Chip Memory : 16 KB
# Total Off Chip Memory : 32 MB
# - SDRAM_8Mx32 = 32 MB
# ##############################################################################
# Parameters
PARAMETER VERSION = 2.1.0
PORT ext_clk = sys_clk, DIR = IN
PORT ddr_clk_fb = ddr_clk_fb, DIR = IN
PORT sys_rst = sys_rst, DIR = IN
PORT console_uart_rx = console_uart_rx, DIR = IN
PORT console_uart_tx = console_uart_tx, DIR = OUT
PORT gpio = gpio, VEC = [0:23], DIR = INOUT
PORT SDRAM_Clk = SDRAM_Clk, DIR = OUT
PORT SDRAM_CKE = SDRAM_CKE, DIR = OUT
PORT SDRAM_CSn = SDRAM_CSn, DIR = OUT
PORT SDRAM_RASn = SDRAM_RASn, DIR = OUT
PORT SDRAM_CASn = SDRAM_CASn, DIR = OUT
PORT SDRAM_WEn = SDRAM_WEn, DIR = OUT
PORT SDRAM_DQM = SDRAM_DQM, DIR = OUT
PORT SDRAM_BankAddr = SDRAM_BankAddr, VEC = [0:1], DIR = OUT
PORT SDRAM_Addr = SDRAM_Addr, VEC = [0:12], DIR = OUT
PORT SDRAM_DQ = SDRAM_DQ, VEC = [0:7], DIR = INOUT
PORT sram_flash_Mem_A = sram_flash_Mem_A, VEC = [31:0], DIR = OUT
PORT sram_flash_Mem_DQ = sram_flash_Mem_DQ, VEC = [0:7], DIR = INOUT
PORT sram_flash_Mem_CEN = sram_flash_Mem_CEN, DIR = OUT
PORT sram_flash_Mem_OEN = sram_flash_Mem_OEN, DIR = OUT
PORT sram_flash_Mem_WEN = sram_flash_Mem_WEN, DIR = OUT
# Sub Components
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
PARAMETER C_USE_MSR_INSTR = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_BASEADDR = 0x80000000
PARAMETER C_ICACHE_HIGHADDR = 0x81FFFFFF
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_ADDR_TAG_BITS = 11
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BASEADDR = 0x80000000
PARAMETER C_DCACHE_HIGHADDR = 0x81FFFFFF
PARAMETER C_DCACHE_BYTE_SIZE = 16384
PARAMETER C_DCACHE_ADDR_TAG = 11
PARAMETER C_FSL_LINKS = 1
BUS_INTERFACE SFSL0 = download_link
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk
PORT INTERRUPT = interrupt
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 0
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0xFFFFC000
PARAMETER C_HIGHADDR = 0xFFFFC0FF
PARAMETER C_WRITE_FSL_PORTS = 1
BUS_INTERFACE MFSL0 = download_link
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
END
BEGIN fsl_v20
PARAMETER INSTANCE = download_link
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst
PORT FSL_Clk = sys_clk
END
BEGIN opb_emc
PARAMETER INSTANCE = sram_flash
PARAMETER HW_VER = 1.10.b
PARAMETER C_BASEADDR = 0xFFFF0000
PARAMETER C_HIGHADDR = 0xFFFF01FF
PARAMETER C_MEM0_BASEADDR = 0xFFE00000
PARAMETER C_MEM0_HIGHADDR = 0xFFEFFFFF
PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 14000
PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 12000
PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 14000
PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 12000
PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 8000
PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 12000
PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 12000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MEM0_WIDTH = 8
PARAMETER C_MAX_MEM_WIDTH = 8
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_OPB_CLK_PERIOD_PS = 40000
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
PORT Mem_A = sram_flash_Mem_A
PORT Mem_DQ = sram_flash_Mem_DQ
PORT Mem_CEN = sram_flash_Mem_CEN
PORT Mem_OEN = sram_flash_Mem_OEN
PORT Mem_WEN = sram_flash_Mem_WEN
END
BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_CLK_FREQ = 25_000_000
PARAMETER C_BASEADDR = 0xFFFF2000
PARAMETER C_HIGHADDR = 0xFFFF20FF
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = console_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = console_uart_rx
PORT TX = console_uart_tx
END
BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff3000
PARAMETER C_HIGHADDR = 0xffff30ff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = interrupt
PORT OPB_Clk = sys_clk
PORT Intr = console_uart_interrupt & timer_interrupt
END
BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff1000
PARAMETER C_HIGHADDR = 0xffff10ff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
PORT Interrupt = timer_interrupt
END
BEGIN opb_gpio
PARAMETER INSTANCE = system_gpio
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0xffff5000
PARAMETER C_HIGHADDR = 0xffff50ff
PARAMETER C_GPIO_WIDTH = 24
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_IO = gpio
PORT OPB_Clk = sys_clk
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = conn_0
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003FFF
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = conn_1
END
BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 16384
BUS_INTERFACE PORTA = conn_0
BUS_INTERFACE PORTB = conn_1
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END
BEGIN opb_sdram
PARAMETER INSTANCE = sdram_controller
PARAMETER HW_VER = 1.00.d
PARAMETER C_BASEADDR = 0x80000000
PARAMETER C_HIGHADDR = 0x81ffffff
PARAMETER C_SDRAM_TRAS = 120000
PARAMETER C_SDRAM_TRC = 66000
PARAMETER C_SDRAM_TRFC = 66000
PARAMETER C_SDRAM_DWIDTH = 8
PARAMETER C_SDRAM_COL_AWIDTH = 10
PARAMETER C_OPB_CLK_PERIOD_PS = 40000
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk
PORT SDRAM_Clk_in = sys_clk
PORT SDRAM_Clk = SDRAM_Clk
PORT SDRAM_CKE = SDRAM_CKE
PORT SDRAM_CSn = SDRAM_CSn
PORT SDRAM_RASn = SDRAM_RASn
PORT SDRAM_CASn = SDRAM_CASn
PORT SDRAM_WEn = SDRAM_WEn
PORT SDRAM_DQM = SDRAM_DQM
PORT SDRAM_BankAddr = SDRAM_BankAddr
PORT SDRAM_Addr = SDRAM_Addr
PORT SDRAM_DQ = SDRAM_DQ
END
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = uclinux
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER MAIN_MEMORY = sdram_controller
PARAMETER LMB_MEMORY = ilmb_cntlr
# handlers for the bootloader, not used in uclinux kernel
PARAMETER STDOUT = console_uart
PARAMETER STDIN = console_uart
END
# where to copy resulting auto-config.in file
# PARAMETER TARGET_DIR = /mnt/home2/jwilliam/dist-test/uClinux-dist/linux-2.4.x/arch/microblaze/platform/uclinux-auto
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER ARCHIVER = mb-ar
PARAMETER COMPILER = mb-gcc
PARAMETER XMDSTUB_PERIPHERAL = debug_module
# 66MHz
PARAMETER CORE_CLOCK_FREQ_HZ = 25000000
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = mb_opb
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.00.c
PARAMETER HW_INSTANCE = system_intc
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = system_timer
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER HW_INSTANCE = console_uart
PARAMETER LEVEL = 0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = system_gpio
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emc
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = sram_flash
PARAMETER LEVEL = 0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = sdram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = sdram_controller
END
PBD VERSION 1
SCHEMATIC VERSION 6
BEGIN SCHEMATIC
BEGIN ATTR DeviceFamilyName
DELETE all:0
EDITNAME all:0
EDITTRAIT all:0
END ATTR
ATTR MhsPort_ext_clk "ext_clk:sys_clk:*:Input:External:Normal:None"
ATTR MhsPort_ddr_clk_fb "ddr_clk_fb:ddr_clk_fb:*:Input:External:Normal:None"
ATTR MhsPort_sys_rst "sys_rst:sys_rst:*:Input:External:Normal:None"
ATTR MhsPort_console_uart_rx "console_uart_rx:console_uart_rx:*:Input:External:Normal:None"
ATTR MhsPort_console_uart_tx "console_uart_tx:console_uart_tx:*:Output:External:Normal:None"
ATTR MhsPort_gpio "gpio:gpio:[0;23]:BiDirectional:External:Normal:None"
ATTR MhsPort_SDRAM_Clk "SDRAM_Clk:SDRAM_Clk:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_CKE "SDRAM_CKE:SDRAM_CKE:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_CSn "SDRAM_CSn:SDRAM_CSn:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_RASn "SDRAM_RASn:SDRAM_RASn:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_CASn "SDRAM_CASn:SDRAM_CASn:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_WEn "SDRAM_WEn:SDRAM_WEn:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_DQM "SDRAM_DQM:SDRAM_DQM:*:Output:External:Normal:None"
ATTR MhsPort_SDRAM_BankAddr "SDRAM_BankAddr:SDRAM_BankAddr:[0;1]:Output:External:Normal:None"
ATTR MhsPort_SDRAM_Addr "SDRAM_Addr:SDRAM_Addr:[0;12]:Output:External:Normal:None"
ATTR MhsPort_SDRAM_DQ "SDRAM_DQ:SDRAM_DQ:[0;7]:BiDirectional:External:Normal:None"
ATTR MhsPort_sram_flash_Mem_A "sram_flash_Mem_A:sram_flash_Mem_A:[31;0]:Output:External:Normal:None"
ATTR MhsPort_sram_flash_Mem_DQ "sram_flash_Mem_DQ:sram_flash_Mem_DQ:[0;7]:BiDirectional:External:Normal:None"
ATTR MhsPort_sram_flash_Mem_CEN "sram_flash_Mem_CEN:sram_flash_Mem_CEN:*:Output:External:Normal:None"
ATTR MhsPort_sram_flash_Mem_OEN "sram_flash_Mem_OEN:sram_flash_Mem_OEN:*:Output:External:Normal:None"
ATTR MhsPort_sram_flash_Mem_WEN "sram_flash_Mem_WEN:sram_flash_Mem_WEN:*:Output:External:Normal:None"
BEGIN NETLIST
BEGIN SIGNAL download_link
ATTR MpdName "fsl_v20"
ATTR MpdHwVersion "2.00.a"
ATTR C_EXT_RESET_HIGH "0"
ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst:*:Input:Internal:Normal:None"
ATTR MhsPort_FSL_Clk "FSL_Clk:sys_clk:*:Input:Internal:Normal:None"
END SIGNAL
BEGIN SIGNAL dlmb
ATTR MpdName "lmb_v10"
ATTR MpdHwVersion "1.00.a"
ATTR C_EXT_RESET_HIGH "0"
ATTR MhsPort_LMB_Clk "LMB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst:*:Input:Internal:Normal:None"
END SIGNAL
BEGIN SIGNAL ilmb
ATTR MpdName "lmb_v10"
ATTR MpdHwVersion "1.00.a"
ATTR C_EXT_RESET_HIGH "0"
ATTR MhsPort_LMB_Clk "LMB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst:*:Input:Internal:Normal:None"
END SIGNAL
BEGIN SIGNAL mb_opb
ATTR MpdName "opb_v20"
ATTR MpdHwVersion "1.10.b"
ATTR C_EXT_RESET_HIGH "0"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_SYS_Rst "SYS_Rst:sys_rst:*:Input:Internal:Normal:None"
END SIGNAL
BEGIN SIGNAL conn_0
ATTR MpdName "Transparent"
ATTR MpdHwVersion "1.00.a"
END SIGNAL
BEGIN SIGNAL conn_1
ATTR MpdName "Transparent"
ATTR MpdHwVersion "1.00.a"
END SIGNAL
BEGIN BLOCKDEF microblaze_0
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 160
LINE N 0 32 32 32
LINE N 128 32 96 32
LINE N 128 64 96 64
LINE N 128 96 96 96
LINE N 128 128 96 128
END BLOCKDEF
BEGIN BLOCKDEF debug_module
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 96
LINE N 0 32 32 32
LINE N 0 64 32 64
END BLOCKDEF
BEGIN BLOCKDEF sram_flash
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 64
LINE N 0 32 32 32
END BLOCKDEF
BEGIN BLOCKDEF console_uart
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 64
LINE N 0 32 32 32
END BLOCKDEF
BEGIN BLOCKDEF system_intc
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 64
LINE N 0 32 32 32
END BLOCKDEF
BEGIN BLOCKDEF system_timer
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 64
LINE N 0 32 32 32
END BLOCKDEF
BEGIN BLOCKDEF system_gpio
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 64
LINE N 0 32 32 32
END BLOCKDEF
BEGIN BLOCKDEF dlmb_cntlr
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 96
LINE N 0 32 32 32
LINE N 0 64 32 64
END BLOCKDEF
BEGIN BLOCKDEF ilmb_cntlr
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 96
LINE N 0 32 32 32
LINE N 0 64 32 64
END BLOCKDEF
BEGIN BLOCKDEF sdram_controller
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 64
LINE N 0 32 32 32
END BLOCKDEF
BEGIN BLOCKDEF bram
TIMESTAMP 2005 4 28 7 40 18
RECTANGLE N 32 0 96 96
LINE N 0 32 32 32
LINE N 0 64 32 64
END BLOCKDEF
BEGIN BLOCK microblaze_0 microblaze_0
ATTR MpdName "microblaze"
ATTR MpdHwVersion "3.00.a"
ATTR C_USE_BARREL "1"
ATTR C_USE_DIV "1"
ATTR C_USE_MSR_INSTR "1"
ATTR C_DEBUG_ENABLED "1"
ATTR C_NUMBER_OF_PC_BRK "2"
ATTR C_NUMBER_OF_RD_ADDR_BRK "1"
ATTR C_NUMBER_OF_WR_ADDR_BRK "1"
ATTR C_USE_ICACHE "1"
ATTR C_ICACHE_BASEADDR "0x80000000"
ATTR C_ICACHE_HIGHADDR "0x81FFFFFF"
ATTR C_CACHE_BYTE_SIZE "16384"
ATTR C_ADDR_TAG_BITS "11"
ATTR C_USE_DCACHE "1"
ATTR C_DCACHE_BASEADDR "0x80000000"
ATTR C_DCACHE_HIGHADDR "0x81FFFFFF"
ATTR C_DCACHE_BYTE_SIZE "16384"
ATTR C_DCACHE_ADDR_TAG "11"
ATTR C_FSL_LINKS "1"
ATTR MhsPort_CLK "CLK:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_INTERRUPT "INTERRUPT:interrupt:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SFSL0:T:R=DLMB,ILMB,DOPB,IOPB:B"
PIN SFSL0 download_link
PIN DLMB dlmb
PIN ILMB ilmb
PIN DOPB mb_opb
PIN IOPB mb_opb
END BLOCK
BEGIN BLOCK debug_module debug_module
ATTR MpdName "opb_mdm"
ATTR MpdHwVersion "2.00.a"
ATTR C_MB_DBG_PORTS "1"
ATTR C_USE_UART "0"
ATTR C_UART_WIDTH "8"
ATTR C_BASEADDR "0xFFFFC000"
ATTR C_HIGHADDR "0xFFFFC0FF"
ATTR C_WRITE_FSL_PORTS "1"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=MFSL0,SOPB:T:R:B"
PIN MFSL0 download_link
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK sram_flash sram_flash
ATTR MpdName "opb_emc"
ATTR MpdHwVersion "1.10.b"
ATTR C_BASEADDR "0xFFFF0000"
ATTR C_HIGHADDR "0xFFFF01FF"
ATTR C_MEM0_BASEADDR "0xFFE00000"
ATTR C_MEM0_HIGHADDR "0xFFEFFFFF"
ATTR C_MEM1_BASEADDR "0xFF000000"
ATTR C_MEM1_HIGHADDR "0xFF7FFFFF"
ATTR C_WRITE_ADDR_TO_OUT_SLOW_PS_0 "14000"
ATTR C_WRITE_MIN_PULSE_WIDTH_PS_0 "12000"
ATTR C_READ_ADDR_TO_OUT_SLOW_PS_0 "14000"
ATTR C_READ_ADDR_TO_OUT_FAST_PS_0 "12000"
ATTR C_WRITE_ADDR_TO_OUT_FAST_PS_0 "8000"
ATTR C_READ_RECOVERY_BEFORE_WRITE_PS_0 "12000"
ATTR C_WRITE_RECOVERY_BEFORE_READ_PS_0 "12000"
ATTR C_NUM_BANKS_MEM "1"
ATTR C_MEM0_WIDTH "8"
ATTR C_MAX_MEM_WIDTH "8"
ATTR C_INCLUDE_DATAWIDTH_MATCHING_0 "1"
ATTR C_SYNCH_MEM_0 "0"
ATTR C_OPB_CLK_PERIOD_PS "40000"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_Mem_A "Mem_A:sram_flash_Mem_A:*:Input:Internal:Normal:None"
ATTR MhsPort_Mem_DQ "Mem_DQ:sram_flash_Mem_DQ:*:Input:Internal:Normal:None"
ATTR MhsPort_Mem_CEN "Mem_CEN:sram_flash_Mem_CEN:*:Input:Internal:Normal:None"
ATTR MhsPort_Mem_OEN "Mem_OEN:sram_flash_Mem_OEN:*:Input:Internal:Normal:None"
ATTR MhsPort_Mem_WEN "Mem_WEN:sram_flash_Mem_WEN:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK console_uart console_uart
ATTR MpdName "opb_uartlite"
ATTR MpdHwVersion "1.00.b"
ATTR C_BAUDRATE "57600"
ATTR C_DATA_BITS "8"
ATTR C_USE_PARITY "0"
ATTR C_ODD_PARITY "0"
ATTR C_CLK_FREQ "25_000_000"
ATTR C_BASEADDR "0xFFFF2000"
ATTR C_HIGHADDR "0xFFFF20FF"
ATTR MhsPort_Interrupt "Interrupt:console_uart_interrupt:*:Input:Internal:Normal:None"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_RX "RX:console_uart_rx:*:Input:Internal:Normal:None"
ATTR MhsPort_TX "TX:console_uart_tx:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK system_intc system_intc
ATTR MpdName "opb_intc"
ATTR MpdHwVersion "1.00.c"
ATTR C_BASEADDR "0xffff3000"
ATTR C_HIGHADDR "0xffff30ff"
ATTR MhsPort_Irq "Irq:interrupt:*:Input:Internal:Normal:None"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_Intr "Intr:console_uart_interrupt & timer_interrupt:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK system_timer system_timer
ATTR MpdName "opb_timer"
ATTR MpdHwVersion "1.00.b"
ATTR C_BASEADDR "0xffff1000"
ATTR C_HIGHADDR "0xffff10ff"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_Interrupt "Interrupt:timer_interrupt:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK system_gpio system_gpio
ATTR MpdName "opb_gpio"
ATTR MpdHwVersion "2.00.a"
ATTR C_BASEADDR "0xffff5000"
ATTR C_HIGHADDR "0xffff50ff"
ATTR C_GPIO_WIDTH "24"
ATTR MhsPort_GPIO_IO "GPIO_IO:gpio:*:Input:Internal:Normal:None"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK dlmb_cntlr dlmb_cntlr
ATTR MpdName "lmb_bram_if_cntlr"
ATTR MpdHwVersion "1.00.b"
ATTR C_BASEADDR "0x00000000"
ATTR C_HIGHADDR "0x00003FFF"
ATTR MpdSymbolInstructions "W64:H64:L=SLMB,BRAM_PORT:T:R:B"
PIN SLMB dlmb
PIN BRAM_PORT conn_0
END BLOCK
BEGIN BLOCK ilmb_cntlr ilmb_cntlr
ATTR MpdName "lmb_bram_if_cntlr"
ATTR MpdHwVersion "1.00.b"
ATTR C_BASEADDR "0x00000000"
ATTR C_HIGHADDR "0x00003FFF"
ATTR MpdSymbolInstructions "W64:H64:L=SLMB,BRAM_PORT:T:R:B"
PIN SLMB ilmb
PIN BRAM_PORT conn_1
END BLOCK
BEGIN BLOCK sdram_controller sdram_controller
ATTR MpdName "opb_sdram"
ATTR MpdHwVersion "1.00.d"
ATTR C_BASEADDR "0x80000000"
ATTR C_HIGHADDR "0x81ffffff"
ATTR C_SDRAM_TRAS "120000"
ATTR C_SDRAM_TRC "66000"
ATTR C_SDRAM_TRFC "66000"
ATTR C_SDRAM_DWIDTH "8"
ATTR C_SDRAM_COL_AWIDTH "10"
ATTR C_OPB_CLK_PERIOD_PS "40000"
ATTR MhsPort_OPB_Clk "OPB_Clk:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_Clk_in "SDRAM_Clk_in:sys_clk:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_Clk "SDRAM_Clk:SDRAM_Clk:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_CKE "SDRAM_CKE:SDRAM_CKE:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_CSn "SDRAM_CSn:SDRAM_CSn:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_RASn "SDRAM_RASn:SDRAM_RASn:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_CASn "SDRAM_CASn:SDRAM_CASn:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_WEn "SDRAM_WEn:SDRAM_WEn:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_DQM "SDRAM_DQM:SDRAM_DQM:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_BankAddr "SDRAM_BankAddr:SDRAM_BankAddr:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_Addr "SDRAM_Addr:SDRAM_Addr:*:Input:Internal:Normal:None"
ATTR MhsPort_SDRAM_DQ "SDRAM_DQ:SDRAM_DQ:*:Input:Internal:Normal:None"
ATTR MpdSymbolInstructions "W64:H64:L=SOPB:T:R:B"
PIN SOPB mb_opb
END BLOCK
BEGIN BLOCK bram bram
ATTR MpdName "bram_block"
ATTR MpdHwVersion "1.00.a"
ATTR C_MEMSIZE "16384"
ATTR MpdSymbolInstructions "W64:H64:L=PORTA,PORTB:T:R:B"
PIN PORTA conn_0
PIN PORTB conn_1
END BLOCK
END NETLIST
BEGIN SHEET 1 1440 1424
BEGIN BRANCH download_link
WIRE 48 48 48 160
WIRE 48 160 80 160
WIRE 48 160 48 352
WIRE 48 352 48 1376
WIRE 48 352 656 352
BEGIN DISPLAY 48 48 ATTR Name
ALIGNMENT HARD-BCENTER
END DISPLAY
BEGIN DISPLAY 48 1376 ATTR Name
ALIGNMENT HARD-TCENTER
END DISPLAY
END BRANCH
BEGIN BRANCH dlmb
WIRE 208 160 240 160
WIRE 240 160 240 1056
WIRE 240 1056 240 1376
WIRE 240 1056 848 1056
WIRE 240 48 240 160
BEGIN DISPLAY 240 48 ATTR Name
ALIGNMENT HARD-BCENTER
END DISPLAY
BEGIN DISPLAY 240 1376 ATTR Name
ALIGNMENT HARD-TCENTER
END DISPLAY
END BRANCH
BEGIN BRANCH ilmb
WIRE 208 192 432 192
WIRE 432 192 432 1184
WIRE 432 1184 432 1376
WIRE 432 1184 1040 1184
WIRE 432 48 432 192
BEGIN DISPLAY 432 48 ATTR Name
ALIGNMENT HARD-BCENTER
END DISPLAY
BEGIN DISPLAY 432 1376 ATTR Name
ALIGNMENT HARD-TCENTER
END DISPLAY
END BRANCH
BEGIN BRANCH mb_opb
WIRE 208 224 624 224
WIRE 624 224 624 256
WIRE 624 256 624 384
WIRE 624 384 656 384
WIRE 624 384 624 480
WIRE 624 480 656 480
WIRE 624 480 624 672
WIRE 624 672 656 672
WIRE 624 672 624 768
WIRE 624 768 656 768
WIRE 624 768 624 864
WIRE 624 864 656 864
WIRE 624 864 624 960
WIRE 624 960 656 960
WIRE 624 960 624 1312
WIRE 624 1312 624 1376
WIRE 624 1312 656 1312
WIRE 208 256 624 256
WIRE 624 48 624 224
BEGIN DISPLAY 624 48 ATTR Name
ALIGNMENT HARD-BCENTER
END DISPLAY
BEGIN DISPLAY 624 1376 ATTR Name
ALIGNMENT HARD-TCENTER
END DISPLAY
END BRANCH
BEGIN BRANCH conn_0
WIRE 816 48 816 352
WIRE 816 352 816 1088
WIRE 816 1088 816 1376
WIRE 816 1088 848 1088
WIRE 816 352 1040 352
BEGIN DISPLAY 816 48 ATTR Name
ALIGNMENT HARD-BCENTER
END DISPLAY
BEGIN DISPLAY 816 1376 ATTR Name
ALIGNMENT HARD-TCENTER
END DISPLAY
END BRANCH
BEGIN BRANCH conn_1
WIRE 1008 48 1008 384
WIRE 1008 384 1008 1216
WIRE 1008 1216 1008 1376
WIRE 1008 1216 1040 1216
WIRE 1008 384 1040 384
BEGIN DISPLAY 1008 48 ATTR Name
ALIGNMENT HARD-BCENTER
END DISPLAY
BEGIN DISPLAY 1008 1376 ATTR Name
ALIGNMENT HARD-TCENTER
END DISPLAY
END BRANCH
INSTANCE microblaze_0 80 128 R0
INSTANCE debug_module 656 320 R0
INSTANCE sram_flash 656 448 R0
INSTANCE console_uart 656 640 R0
INSTANCE system_intc 656 736 R0
INSTANCE system_timer 656 832 R0
INSTANCE system_gpio 656 928 R0
INSTANCE dlmb_cntlr 848 1024 R0
INSTANCE ilmb_cntlr 1040 1152 R0
INSTANCE sdram_controller 656 1280 R0
INSTANCE bram 1040 320 R0
END SHEET
END SCHEMATIC
###############################################################################
# Pin Assignments
###############################################################################
# external 25MHz oscillator
NET "sys_clk" LOC = "C11";
# external reset pin (push 2). Active low
NET "sys_rst" LOC = "A15";
NET "sys_rst" PULLUP;
# stdio uart tx/rx goes to the main board RS232 driver
NET "console_uart_tx" LOC = "A7";
NET "console_uart_rx" LOC = "B7";
#SRAM
NET "sram_flash_Mem_CEN" LOC = "P22";
NET "sram_flash_Mem_CEN" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_CEN" DRIVE = 12;
NET "sram_flash_Mem_WEN" LOC = "N22";
NET "sram_flash_Mem_WEN" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_WEN" DRIVE = 12;
NET "sram_flash_Mem_OEN" LOC = "T19";
NET "sram_flash_Mem_OEN" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_OEN" DRIVE = 12;
NET "sram_flash_Mem_A<0>" LOC = "R19";
NET "sram_flash_Mem_A<0>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<0>" DRIVE = 12;
NET "sram_flash_Mem_A<1>" LOC = "R21";
NET "sram_flash_Mem_A<1>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<1>" DRIVE = 12;
NET "sram_flash_Mem_A<2>" LOC = "R20";
NET "sram_flash_Mem_A<2>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<2>" DRIVE = 12;
NET "sram_flash_Mem_A<3>" LOC = "P17";
NET "sram_flash_Mem_A<3>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<3>" DRIVE = 12;
NET "sram_flash_Mem_A<4>" LOC = "P18";
NET "sram_flash_Mem_A<4>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<4>" DRIVE = 12;
NET "sram_flash_Mem_A<5>" LOC = "N18";
NET "sram_flash_Mem_A<5>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<5>" DRIVE = 12;
NET "sram_flash_Mem_A<6>" LOC = "N19";
NET "sram_flash_Mem_A<6>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<6>" DRIVE = 12;
NET "sram_flash_Mem_A<7>" LOC = "N21";
NET "sram_flash_Mem_A<7>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<7>" DRIVE = 12;
NET "sram_flash_Mem_A<8>" LOC = "N20";
NET "sram_flash_Mem_A<8>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<8>" DRIVE = 12;
NET "sram_flash_Mem_A<9>" LOC = "M17";
NET "sram_flash_Mem_A<9>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<9>" DRIVE = 12;
NET "sram_flash_Mem_A<10>" LOC = "AB19";
NET "sram_flash_Mem_A<10>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<10>" DRIVE = 12;
NET "sram_flash_Mem_A<11>" LOC = "AA12";
NET "sram_flash_Mem_A<11>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<11>" DRIVE = 12;
NET "sram_flash_Mem_A<12>" LOC = "AA14";
NET "sram_flash_Mem_A<12>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<12>" DRIVE = 12;
NET "sram_flash_Mem_A<13>" LOC = "AA15";
NET "sram_flash_Mem_A<13>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<13>" DRIVE = 12;
NET "sram_flash_Mem_A<14>" LOC = "AA16";
NET "sram_flash_Mem_A<14>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<14>" DRIVE = 12;
NET "sram_flash_Mem_A<15>" LOC = "T21";
NET "sram_flash_Mem_A<15>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<15>" DRIVE = 12;
NET "sram_flash_Mem_A<16>" LOC = "T20";
NET "sram_flash_Mem_A<16>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<16>" DRIVE = 12;
NET "sram_flash_Mem_A<17>" LOC = "R18";
NET "sram_flash_Mem_A<17>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<17>" DRIVE = 12;
NET "sram_flash_Mem_A<18>" LOC = "R22";
NET "sram_flash_Mem_A<18>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_A<18>" DRIVE = 12;
NET "sram_flash_Mem_DQ<0>" LOC = "P19";
NET "sram_flash_Mem_DQ<0>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<0>" DRIVE = 12;
NET "sram_flash_Mem_DQ<1>" LOC = "P21";
NET "sram_flash_Mem_DQ<1>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<1>" DRIVE = 12;
NET "sram_flash_Mem_DQ<2>" LOC = "P20";
NET "sram_flash_Mem_DQ<2>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<2>" DRIVE = 12;
NET "sram_flash_Mem_DQ<3>" LOC = "N17";
NET "sram_flash_Mem_DQ<3>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<3>" DRIVE = 12;
NET "sram_flash_Mem_DQ<4>" LOC = "W12";
NET "sram_flash_Mem_DQ<4>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<4>" DRIVE = 12;
NET "sram_flash_Mem_DQ<5>" LOC = "V13";
NET "sram_flash_Mem_DQ<5>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<5>" DRIVE = 12;
NET "sram_flash_Mem_DQ<6>" LOC = "U13";
NET "sram_flash_Mem_DQ<6>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<6>" DRIVE = 12;
NET "sram_flash_Mem_DQ<7>" LOC = "T22";
NET "sram_flash_Mem_DQ<7>" IOSTANDARD = LVTTL;
NET "sram_flash_Mem_DQ<7>" DRIVE = 12;
# gpio
# left LEDs
NET "gpio<0>" LOC = "D9";
NET "gpio<1>" LOC = "C9";
NET "gpio<2>" LOC = "F11";
NET "gpio<3>" LOC = "F9";
NET "gpio<4>" LOC = "F10";
NET "gpio<5>" LOC = "D10";
NET "gpio<6>" LOC = "C10";
NET "gpio<7>" LOC = "M2"; # fake pin, LOC on lvds header
#right LEDs
NET "gpio<8>" LOC = "B9";
NET "gpio<9>" LOC = "A8";
NET "gpio<10>" LOC = "B8";
NET "gpio<11>" LOC = "E7";
NET "gpio<12>" LOC = "E8";
NET "gpio<13>" LOC = "E10";
NET "gpio<14>" LOC = "E9";
# user LED, use as power indicator
NET "gpio<15>" LOC = "A9";
#DIP switches
NET "gpio<16>" LOC = "C6"; # sw 8
NET "gpio<17>" LOC = "D6"; # sw 7
NET "gpio<18>" LOC = "A5"; # ...
NET "gpio<19>" LOC = "B5";
NET "gpio<20>" LOC = "C5";
NET "gpio<21>" LOC = "C4";
NET "gpio<22>" LOC = "A4"; # sw 2
NET "gpio<23>" LOC = "B4"; # sw 1
# SDRAM
NET "SDRAM_CKE" LOC = "Y8";
NET "SDRAM_CSn" LOC = "T1";
NET "SDRAM_RASn" LOC = "T3";
NET "SDRAM_CASn" LOC = "T5";
NET "SDRAM_WEn" LOC = "V5";
NET "SDRAM_DQM" LOC = "W7";
NET "SDRAM_Clk" LOC = "Y10";
NET "SDRAM_BankAddr<0>" LOC = "R2";
NET "SDRAM_BankAddr<1>" LOC = "R4";
NET "SDRAM_DQ<7>" LOC = "U2";
NET "SDRAM_DQ<6>" LOC = "U4";
NET "SDRAM_DQ<5>" LOC = "V1";
NET "SDRAM_DQ<4>" LOC = "V3";
NET "SDRAM_DQ<3>" LOC = "AA7";
NET "SDRAM_DQ<2>" LOC = "V8";
NET "SDRAM_DQ<1>" LOC = "U19";
NET "SDRAM_DQ<0>" LOC = "U18";
NET "SDRAM_Addr<12>" LOC = "Y2";
NET "SDRAM_Addr<11>" LOC = "P2";
NET "SDRAM_Addr<10>" LOC = "N6";
NET "SDRAM_Addr<9>" LOC = "N4";
NET "SDRAM_Addr<8>" LOC = "Y11";
NET "SDRAM_Addr<7>" LOC = "V11";
NET "SDRAM_Addr<6>" LOC = "AB10";
NET "SDRAM_Addr<5>" LOC = "V10";
NET "SDRAM_Addr<4>" LOC = "AB9";
NET "SDRAM_Addr<3>" LOC = "Y9";
NET "SDRAM_Addr<2>" LOC = "P6";
NET "SDRAM_Addr<1>" LOC = "V9";
NET "SDRAM_Addr<0>" LOC = "AB8";