Re: [microblaze-uclinux] Storage Device Driver Development

[Rudolf Usselmann <rudi@xxxxxxxx>]

On Wed, 2005-05-11 at 10:53 +0200, Claudio Lanconelli wrote:
> Rudolf Usselmann wrote:
> 
> >Our IP Core does all the low level protocols in Hardware. The
> >cards come up as memory mapped. It will automatically select
> >the highest supported protocol, up to 8 bit for the new MMC
> >cards. I have written a boot loader based on the xilinx fat
> >fs libraries - basically just writing a read_sector function
> >and than opening a file using the xilinx library and copying
> >the file to SDRAM and executing it. Very trivial.
> >
> >Now it would be nice to have a device driver for ucLinux that
> >would have the same type of interface. That should help to have
> >any memory mapped boot device mountable ...
> >  
> >
> Hi Rudolf,
> it's very interesting.
> Some questions:
> Is your IP core connected to OPB bus?

Yes it can be. We provide OPB bus interface as one option.

> Does your core provide an interrupt transfer mode? Interrupt per sector 
> or interrupt per byte or other?

A memory card (SD or MMC) is memory mapped. You define a
window and move that window across the cards total memory.
The internal architecture is such that we cash the 8 last
accessed blocks.

There are several different ways of operations:
1) interrupt driven - you get an interrupt if a page has
   been loaded, and/or if the last read was a hit/miss.
2) Bus is kept locked (e.g. ack delayed)   until the data
   has been fetched from the card
3) You get a retry acknowledge

This is juast a brief summary of some options. It all supports
ATA over MMC, streaming and all other features defined by the
spec.

> Is your core freely available to test?

Not, really, it is a commercial product. Contact me privately
and we can discuss various options to evaluate the IP.

> Regards,
> Claudio Lanconelli

Best Regards 
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

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