RE: [microblaze-uclinux] mixed EDK and ISE projects

["Kristian Chaplin" <kristian.chaplin@xxxxxxxxxx>]

Hi John,

You're right - if you are to re-run Export to Projnav, then the 
<project>_stub file would be overwritten.  When using the export to
projnav 
flow, I always describe <project>_stub as "An example instantiation of
the 
system".  If you use this flow, I recommend renaming the file to avoid 
frustration.  Think of it as a language template for your toplevel
(albeit a 
fully synthesizable one)!

Moving forward, If intending to integrate with other FPGA logic, I would

recommend using ISE to generate the EDK project (You create the project
as a 
new source file, just like a VHDL or Verilog source).  Make sure your
ISE 
project is targeted at the correct FPGA part, create a new EDK project
from 
the project-> new source menu and carry on from there.  The base system 
builder can be started, and will only provide details on boards based on
the 
part selected in your project.  When instantiating the toplevel, select
the 
EDK "block" and select "view HDL instantiation template",(brings up 
<project>_stub.vhd), and save this / copy sections into your toplevel.


Of course, if you make modifications to the EDK project that affect the 
ports of the processor subsystem, modifications to your instantiation
would 
be required.

Best regards

Kris
--
------------------------------------------------------------------------
----
/ /\/ Kris Chaplin
\ \   Applications Engineer - Embedded Processors
/ /   Xilinx Europe
\_\/\ +44 (0)870-7356-563

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au
[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of John
Williams
Sent: 17 May 2005 07:00
To: microblaze-uclinux@itee.uq.edu.au
Subject: [microblaze-uclinux] mixed EDK and ISE projects

Hi everyone,

Previously I've worked mostly with EDK generating and synthesising the 
top level designs, but am now looking into the combined EDK+ISE flow. 
This is primarily for integrating custom cores that do not wrap nicely 
within the EDK pcores structure.

I used EDK to create my main MicroBlaze system, with the "heirarchy and 
flow" project options identifying it as a submodule, and to use the ISE 
flow.  This created a couple of VHDL files and a ProjNav project:

* system.vhd - the microblaze system wrapper

* system-stub.vhd - a true toplevel vhdl file, which instantiates the 
microblaze subsystem

* The ISE project file defaults to using the system-stub as the top
level.

Two facts (or observations at least):

1. These files are overwritten each time you run "tools->export to 
ProjNav" from XPS.

2. The purpose of using ISE for toplevel synthesis implies that wou will

be modifying the system-stub.vhd and ProjNav project file, ven if only 
trivially.

These two facts suggest that the export EDK project to ProjNav is really

a one-way process.   If you make any change to the EDK projec, 
re-exporting will cause any changes at the top level (system-stub.vhd) 
to be lost.  Also last are any changes to the actual ProjNav project.

Once you add the UCF and ELF files into the ISE project (as per Xilinx 
documentation), they too will be lost after running the "export to 
ProjNav" in XPS.

What is the recommended approach here if you want to develop both the 
toplevel (ISE) design as well as the EDK project?  Copy/rename the 
system-stub.vhd and projnav files, then just cut and paste any changes 
which are subsequently exported from XPS?

Any suggestions or clarifications would be greatly appreciated.

Thanks,

John
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