Hi Wade,
Thanks for the clarification.
Looking at your MHS file, you have 4 banks of memory
Bank 0 -> 0x80000000 2 Meg 16-bit wide Datawidth matching on
Bank 1 -> 0x80200000 2 Meg 16-bit wide Datawidth matching on
Bank 2 -> 0xFF000000 8 Meg 16-bit wide Datawidth matching off
Bank 3 -> 0xFF800000 8 Meg 16-bit wide Datawidth matching off
Banks 2 and 3 are not 32-bit, and do not have data width matching, so
program code cannot be executed from here. Additionally, 32-bit writes
to
these devices will not work, only 16 bits will be stored.
Banks 0 and 1 do have data width matching, so should work for
instructions.
And 32-bit read and write transactions.
I ran through a simulation performing 32, 16 and 8 bit writes to the ram
for
each of the banks - see my attached picture for the output.
What we can see is for the two banks with datawidth matching on, there
are
in actual fact two writes each time. However, the byte enable signals
are
used to totally invalidate one of the transactions in the case of a 16
bit
transaction, and for the 8-bit transaction, select which byte is being
written. Perhaps the waveform will illustrate this better - it is the
output for the following C:
#include <xio.h>
#include <xparameters.h>
void main(void)
{
XIo_Out32(XPAR_SYSTEM_MEMCON_MEM0_BASEADDR, 0x1234);
XIo_Out16(XPAR_SYSTEM_MEMCON_MEM0_BASEADDR, 0x56);
XIo_Out8(XPAR_SYSTEM_MEMCON_MEM0_BASEADDR, 0x7);
XIo_Out32(XPAR_SYSTEM_MEMCON_MEM1_BASEADDR, 0x1234);
XIo_Out16(XPAR_SYSTEM_MEMCON_MEM1_BASEADDR, 0x56);
XIo_Out8(XPAR_SYSTEM_MEMCON_MEM1_BASEADDR, 0x7);
XIo_Out32(XPAR_SYSTEM_MEMCON_MEM2_BASEADDR, 0x1234);
XIo_Out16(XPAR_SYSTEM_MEMCON_MEM2_BASEADDR, 0x56);
XIo_Out8(XPAR_SYSTEM_MEMCON_MEM2_BASEADDR, 0x7);
XIo_Out32(XPAR_SYSTEM_MEMCON_MEM3_BASEADDR, 0x1234);
XIo_Out16(XPAR_SYSTEM_MEMCON_MEM3_BASEADDR, 0x56);
XIo_Out8(XPAR_SYSTEM_MEMCON_MEM3_BASEADDR, 0x7);
}
By not using the byte enables, we cannot distinguish the dead cycles in
the
EMC data width matching from the valid ones.
I hope this helps.
Best regards
Kris
--
------------------------------------------------------------------------
----
/ /\/ Kris Chaplin
\ \ Applications Engineer - Embedded Processors
/ / Xilinx Europe
\_\/\ +44 (0)870-7356-563
-----Original Message-----
From: Wade.Maxfield@precision-es.com
[mailto:Wade.Maxfield@precision-es.com]
Sent: 20 May 2005 17:19
To: microblaze-uclinux@itee.uq.edu.au
Cc: kristian.chaplin
Subject: RE: [microblaze-uclinux] external ram not executing code
Hi,
We are using the OPB_EMC.
Attached is the MHS file, and the UCF file.
The engineer said to let you know that we are Not using CE, (we
are
using CEN), and we aren't using BEN. (Chip Enable, Chip Enable Not,
Byte
Enable Not).
If we write a byte to external memory, we blow away 24 bits of
data
at that long word location. Same way with 16 bits, we blow away the long
word.
I'm now at a point where I have to rely on others for "eyewitness"
accounts, it can get murky due to that. I'm trying to boil down to most
useful information.
Thanks for the help!
wade
(See attached file: system.mhs)(See attached file: system.ucf)
"Kristian
Chaplin"
<kristian.chaplin
To
@xilinx.com>
<microblaze-uclinux@itee.uq.edu.au>
Sent by:
cc
owner-microblaze- "Kristian Chaplin"
uclinux@itee.uq.e <kristian.chaplin@xilinx.com>
du.au
Subject
RE: [microblaze-uclinux] external
ram not executing code
05/19/2005 12:41
PM
Please respond to
microblaze-uclinu
x@itee.uq.edu.au
Hello Wade,
I'm not quite sure what you are seeing here.
I assume if the hardware is SRAM, you are using the OPB_EMC.
What do you mean by it only being 32-bits wide for data? Can you write
8,
16 and 32-bit data values into and out of it?
As the ram is available on the data and instruction side of the bus, you
can
perform some memory test functions. Please tell us what you find.
Also it might be useful to paste in the MHS file for the system, so we
can
check the EMC parameters.
Best regards
Kris
--
------------------------------------------------------------------------
----
/ /\/ Kris Chaplin
\ \ Applications Engineer - Embedded Processors
/ / Xilinx Europe
\_\/\ +44 (0)870-7356-563
-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au
[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of
Wade.Maxfield@precision-es.com
Sent: 19 May 2005 16:53
To: microblaze-uclinux@itee.uq.edu.au
Subject: [microblaze-uclinux] external ram not executing code
My hardware guy is having problems getting external Static Ram to
execute code for the Microblaze. Internal block ram does fine.
As I understand it now, the ram is enabled both for program space
and
data space. However, it appears to only be 32 bits wide for data
(although
it is 2 16 bit wide ram devices).
Any suggestions what to look for?
thanks!
wade
***CONFIDENTIALITY NOTICE***
This communication (and any attachment) is confidential. It should only
be
read by the person(s) to whom
it is addressed. If you have received this communication in error,
please
notify the sender by reply and delete this communication.
*****************************************
***CONFIDENTIALITY NOTICE***
This communication (and any attachment) is confidential. It should only
be
read by the person(s) to whom
it is addressed. If you have received this communication in error,
please
notify the sender by reply and delete this communication.
*****************************************
Attachment:
wave.bmp
Description: wave.bmp
