Hello,
I'm experciencing problem using external SDRAM on
my custom Virtex II
board. I've used a lot of things from Robin Coxe design
:
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2005/03/msg00145.html
but
I still have a last problem. I nearly have the same memory chip as
he does, I
have a 48L32M8A2-75, which means that I have a 8-bit data bus
and he has a
16-bit one. Here is the link for the datasheet :
I have a test program
which is simple and is attached to the email (it
is only a simple version,
the final one will check on more data, but
here I send a simple one for
lisibilty). And here is what I get on the
console :
> Memory Test
Program
> Erasing SDRAM
> Erasing done
> checking
erase
> address : 0x80000000 value : 0x0
> address : 0x80000004
value : 0x0
> address : 0x80000008 value : 0x0
> address :
0x8000000C value : 0x0
> Writing to the SDRAM
> address : 0x80000000
value to be written : 0x12345678
> address : 0x80000004 value to be
written : 0x12345678
> address : 0x80000008 value to be written :
0x12345678
> address : 0x8000000C value to be written : 0x12345678
>
write operations finished
> Reading back from the SDRAM
> address :
0x80000000 read value : 0x345678
> address : 0x80000004 read value :
0x12345678
> address : 0x80000008 read value : 0x345678
> address :
0x8000000C read value : 0x12345678
> end of Memory Test program
As
you can see, I have a problem reading or writing (cannot know it yet)
the
MSbyte, and since Microblaze is big-endian, it must be the last one.
So I think this is a timing problem (maybe am I wrong ? but before I
had the
same behaviour at the same addresses on the two last bytes, and
correcting
timings gave me that better - but still false - behaviour).
I also have to
say that if I shift up the addresses I work with by 4
bytes (one Word) the
addresses where I have problem are the same :
0x.......0 and 0x.......8 :
this is strange !
I've attached my MHS file, but here is the
SDRAM_controller part :
> BEGIN opb_sdram
> PARAMETER
INSTANCE = sdram_controller
> PARAMETER HW_VER =
1.00.d
> PARAMETER C_BASEADDR = 0x80000000
> PARAMETER
C_HIGHADDR = 0x81ffffff
> PARAMETER C_SDRAM_TRAS =
44000
> PARAMETER C_SDRAM_TRC = 66000
> PARAMETER
C_SDRAM_TRFC = 66000
> PARAMETER C_SDRAM_DWIDTH = 8
>
PARAMETER C_OPB_CLK_PERIOD_PS = 15000
> PARAMETER C_SDRAM_COL_AWIDTH
= 10
> PARAMETER C_INCLUDE_BURST_SUPPORT = 0
> PARAMETER
C_SDRAM_TWR = 22500
> PARAMETER C_SDRAM_TMRD = 2
>
PARAMETER C_SDRAM_TCCD = 1
> PARAMETER C_SDRAM_TRCD =
20000
> PARAMETER C_SDRAM_TRRD = 15000
> PARAMETER
C_SDRAM_TRP = 20000
> PARAMETER C_SDRAM_TREF = 64
>
PARAMETER C_SDRAM_CAS_LAT = 2
> PARAMETER C_SDRAM_AWIDTH =
13
> PARAMETER C_SDRAM_BANK_AWIDTH = 2
> PARAMETER
C_SDRAM_TREFI = 7812500
> PARAMETER C_SDRAM_REFRESH_NUMROWS =
8192
> BUS_INTERFACE SOPB = mb_opb
> PORT OPB_Clk =
sys_clk
> PORT SDRAM_Clk_in = sys_clk
> PORT SDRAM_Clk =
SDRAM_Clk
> PORT SDRAM_CKE = SDRAM_CKE
> PORT SDRAM_CSn
= SDRAM_CSn
> PORT SDRAM_RASn = SDRAM_RASn
> PORT
SDRAM_CASn = SDRAM_CASn
> PORT SDRAM_WEn = SDRAM_WEn
>
PORT SDRAM_DQM = SDRAM_DQM
> PORT SDRAM_BankAddr =
SDRAM_BankAddr
> PORT SDRAM_Addr = SDRAM_Addr
> PORT
SDRAM_DQ = SDRAM_DQ
> END
Has someone an idea ?
Thx a
lot
Valentin Longchamp