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Re: [microblaze-uclinux] SDRAM on a Microblaze : I need help

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: Re: [microblaze-uclinux] SDRAM on a Microblaze : I need help
From: Valentin Longchamp <valentin.longchamp@xxxxxxx>
Date: Mon, 30 May 2005 13:51:29 +0200
In-reply-to: <81DEE0885D58274AB59CBAA0CDCD3B3F0A1434@XIR-EXCHVS1.xlnx.xilinx.com>
References: <81DEE0885D58274AB59CBAA0CDCD3B3F0A1434@XIR-EXCHVS1.xlnx.xilinx.com>
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Hello Kristian,

I am talking of the SDRAM controller parameter when I am talking about
timing. By the way, all the timings in the design are met, so I think
the problem is not on that side.

I have gone further in debugging the system, and I've found some clues
that the problem is from writing. I now work with Xuint8 (accessing
bytes individualy) values for debug purpose.

I think I have found an interesting thing : when I only address the
bytes that are causing a problem, here is what I get :

> Memory Test Program
> Erasing SDRAM
> Erasing done
>  checking erase
> address : 0x80000000 value : 0x0
> address : 0x80000008 value : 0x0
> address : 0x80000010 value : 0x0
> address : 0x80000018 value : 0x0
> address : 0x80000020 value : 0x0
> address : 0x80000028 value : 0x0
> address : 0x80000030 value : 0x0
> address : 0x80000038 value : 0x0
> address : 0x80000040 value : 0x0
> address : 0x80000048 value : 0x0
> address : 0x80000050 value : 0x0
> address : 0x80000058 value : 0x0
> address : 0x80000060 value : 0x0
> address : 0x80000068 value : 0x0
> address : 0x80000070 value : 0x0
> address : 0x80000078 value : 0x0
> Writing to the SDRAM
> address : 0x80000000 value to be written : 0x78
> address : 0x80000008 value to be written : 0x78
> address : 0x80000010 value to be written : 0x78
> address : 0x80000018 value to be written : 0x78
> address : 0x80000020 value to be written : 0x78
> address : 0x80000028 value to be written : 0x78
> address : 0x80000030 value to be written : 0x78
> address : 0x80000038 value to be written : 0x78
> address : 0x80000040 value to be written : 0x78
> address : 0x80000048 value to be written : 0x78
> address : 0x80000050 value to be written : 0x78
> address : 0x80000058 value to be written : 0x78
> address : 0x80000060 value to be written : 0x78
> address : 0x80000068 value to be written : 0x78
> address : 0x80000070 value to be written : 0x78
> address : 0x80000078 value to be written : 0x78
> write operations finished
> Reading back from the SDRAM
> address : 0x80000000 read value : 0x78
> address : 0x80000008 read value : 0x78
> address : 0x80000010 read value : 0x78
> address : 0x80000018 read value : 0x78
> address : 0x80000020 read value : 0x78
> address : 0x80000028 read value : 0x78
> address : 0x80000030 read value : 0x78
> address : 0x80000038 read value : 0x78
> address : 0x80000040 read value : 0x78
> address : 0x80000048 read value : 0x78
> address : 0x80000050 read value : 0x78
> address : 0x80000058 read value : 0x78
> address : 0x80000060 read value : 0x78
> address : 0x80000068 read value : 0x78
> address : 0x80000070 read value : 0x78
> address : 0x80000078 read value : 0x78
> end of Memory Test program

So now it seems to be ok. So now I add another access accessing all the
4 values here is what I get :

> Memory Test Program
> Erasing SDRAM
> Erasing done
>  checking erase
> address : 0x80000000 value : 0x0
> address : 0x80000004 value : 0x0
> address : 0x80000008 value : 0x0
> address : 0x8000000C value : 0x0
> address : 0x80000010 value : 0x0
> address : 0x80000014 value : 0x0
> address : 0x80000018 value : 0x0
> address : 0x8000001C value : 0x0
> address : 0x80000020 value : 0x0
> address : 0x80000024 value : 0x0
> address : 0x80000028 value : 0x0
> address : 0x8000002C value : 0x0
> address : 0x80000030 value : 0x0
> address : 0x80000034 value : 0x0
> address : 0x80000038 value : 0x0
> address : 0x8000003C value : 0x0
> Writing to the SDRAM
> address : 0x80000000 value to be written : 0x78
> address : 0x80000004 value to be written : 0x78
> address : 0x80000008 value to be written : 0x78
> address : 0x8000000C value to be written : 0x78
> address : 0x80000010 value to be written : 0x78
> address : 0x80000014 value to be written : 0x78
> address : 0x80000018 value to be written : 0x78
> address : 0x8000001C value to be written : 0x78
> address : 0x80000020 value to be written : 0x78
> address : 0x80000024 value to be written : 0x78
> address : 0x80000028 value to be written : 0x78
> address : 0x8000002C value to be written : 0x78
> address : 0x80000030 value to be written : 0x78
> address : 0x80000034 value to be written : 0x78
> address : 0x80000038 value to be written : 0x78
> address : 0x8000003C value to be written : 0x78
> write operations finished
> Reading back from the SDRAM
> address : 0x80000000 read value : 0x0
> address : 0x80000004 read value : 0x78
> address : 0x80000008 read value : 0x0
> address : 0x8000000C read value : 0x78
> address : 0x80000010 read value : 0x0
> address : 0x80000014 read value : 0x78
> address : 0x80000018 read value : 0x0
> address : 0x8000001C read value : 0x78
> address : 0x80000020 read value : 0x0
> address : 0x80000024 read value : 0x78
> address : 0x80000028 read value : 0x0
> address : 0x8000002C read value : 0x78
> address : 0x80000030 read value : 0x0
> address : 0x80000034 read value : 0x78
> address : 0x80000038 read value : 0x0
> address : 0x8000003C read value : 0x78
> end of Memory Test program

So the other access is actually overwriting the access before !!!! I
think this is my problem ... And as you can see looking at the two next
logs (and the ones from my previous message to the board) is that it
only makes that to the 0 or 8 addresses (or the MSbyte every 2 32 bytes
addresses) :

> Memory Test Program
> Erasing SDRAM
> Erasing done
>  checking erase
> address : 0x80000000 value : 0x0
> address : 0x80000002 value : 0x0
> address : 0x80000004 value : 0x0
> address : 0x80000006 value : 0x0
> address : 0x80000008 value : 0x0
> address : 0x8000000A value : 0x0
> address : 0x8000000C value : 0x0
> address : 0x8000000E value : 0x0
> address : 0x80000010 value : 0x0
> address : 0x80000012 value : 0x0
> address : 0x80000014 value : 0x0
> address : 0x80000016 value : 0x0
> address : 0x80000018 value : 0x0
> address : 0x8000001A value : 0x0
> address : 0x8000001C value : 0x0
> address : 0x8000001E value : 0x0
> Writing to the SDRAM
> address : 0x80000000 value to be written : 0x78
> address : 0x80000002 value to be written : 0x78
> address : 0x80000004 value to be written : 0x78
> address : 0x80000006 value to be written : 0x78
> address : 0x80000008 value to be written : 0x78
> address : 0x8000000A value to be written : 0x78
> address : 0x8000000C value to be written : 0x78
> address : 0x8000000E value to be written : 0x78
> address : 0x80000010 value to be written : 0x78
> address : 0x80000012 value to be written : 0x78
> address : 0x80000014 value to be written : 0x78
> address : 0x80000016 value to be written : 0x78
> address : 0x80000018 value to be written : 0x78
> address : 0x8000001A value to be written : 0x78
> address : 0x8000001C value to be written : 0x78
> address : 0x8000001E value to be written : 0x78
> write operations finished
> Reading back from the SDRAM
> address : 0x80000000 read value : 0x0
> address : 0x80000002 read value : 0x78
> address : 0x80000004 read value : 0x78
> address : 0x80000006 read value : 0x78
> address : 0x80000008 read value : 0x0
> address : 0x8000000A read value : 0x78
> address : 0x8000000C read value : 0x78
> address : 0x8000000E read value : 0x78
> address : 0x80000010 read value : 0x0
> address : 0x80000012 read value : 0x78
> address : 0x80000014 read value : 0x78
> address : 0x80000016 read value : 0x78
> address : 0x80000018 read value : 0x0
> address : 0x8000001A read value : 0x78
> address : 0x8000001C read value : 0x78
> address : 0x8000001E read value : 0x78
> end of Memory Test program

> Memory Test Program
> Erasing SDRAM
> Erasing done
>  checking erase
> address : 0x80000000 value : 0x0
> address : 0x80000001 value : 0x0
> address : 0x80000002 value : 0x0
> address : 0x80000003 value : 0x0
> address : 0x80000004 value : 0x0
> address : 0x80000005 value : 0x0
> address : 0x80000006 value : 0x0
> address : 0x80000007 value : 0x0
> address : 0x80000008 value : 0x0
> address : 0x80000009 value : 0x0
> address : 0x8000000A value : 0x0
> address : 0x8000000B value : 0x0
> address : 0x8000000C value : 0x0
> address : 0x8000000D value : 0x0
> address : 0x8000000E value : 0x0
> address : 0x8000000F value : 0x0
> Writing to the SDRAM
> address : 0x80000000 value to be written : 0x78
> address : 0x80000001 value to be written : 0x78
> address : 0x80000002 value to be written : 0x78
> address : 0x80000003 value to be written : 0x78
> address : 0x80000004 value to be written : 0x78
> address : 0x80000005 value to be written : 0x78
> address : 0x80000006 value to be written : 0x78
> address : 0x80000007 value to be written : 0x78
> address : 0x80000008 value to be written : 0x78
> address : 0x80000009 value to be written : 0x78
> address : 0x8000000A value to be written : 0x78
> address : 0x8000000B value to be written : 0x78
> address : 0x8000000C value to be written : 0x78
> address : 0x8000000D value to be written : 0x78
> address : 0x8000000E value to be written : 0x78
> address : 0x8000000F value to be written : 0x78
> write operations finished
> Reading back from the SDRAM
> address : 0x80000000 read value : 0x0
> address : 0x80000001 read value : 0x78
> address : 0x80000002 read value : 0x78
> address : 0x80000003 read value : 0x78
> address : 0x80000004 read value : 0x78
> address : 0x80000005 read value : 0x78
> address : 0x80000006 read value : 0x78
> address : 0x80000007 read value : 0x78
> address : 0x80000008 read value : 0x0
> address : 0x80000009 read value : 0x78
> address : 0x8000000A read value : 0x78
> address : 0x8000000B read value : 0x78
> address : 0x8000000C read value : 0x78
> address : 0x8000000D read value : 0x78
> address : 0x8000000E read value : 0x78
> address : 0x8000000F read value : 0x78
> end of Memory Test program

All this looks very strange to me ... I have also tried with volatile
memory addresses, but this doesn't change anything at all, and it's
normal ... And I don't think there is an endian'ness problem because the
thing is working great with 7 bytes out of 8 (and not 3 out of 4) ...

So now I have taken the logical analyzer and I'm going to low-level
debug the write sequences, but if someone has an idea and can get me out
of this painful work, it would be great

Tanks in advance

Valentin

Kristian Chaplin wrote:
> Hello Valentin,
>  
> You mention timing.  Would this be timing of the SDRAM controller
> parameters, or timing of the FPGA
> clock constraints?
>  
> A few things to initially check:
>  
> (a) Ensure that the endian'ness of the signals are correct - the OPB is
> big endian, the SDRAM is little endian
> (b) Check that the FPGA design has a UCF file that is properly
> constraining the design (period constraints,
> offset in, offset out etc), * and that the design is meeting timing * -
> Check the end of PAR or use Timing
> Analyser if you are not sure
> (c) Painful, but essential really - It might be worth running a
> simulation to confirm core timing against the datasheet
>  
> Best regards
>  
> Kris
>  
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