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[microblaze-uclinux] Failing uClinux build - what am I missing?

To: <microblaze-uclinux@xxxxxxxxxxxxxx>
Subject: [microblaze-uclinux] Failing uClinux build - what am I missing?
From: "Bruce Karsten" <bruce.karsten@xxxxxxxxxx>
Date: Tue, 14 Jun 2005 23:00:29 -0700
Cc: "Bruce Karsten" <bruce.karsten@xxxxxxxxxx>
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
Thread-index: AcVxb4Z/vmA/R4EiQY+5ie/7zWDeKw==
Thread-topic: Failing uClinux build - what am I missing?



WinXP Machine - This has ISE 6.3.3 & EDK 6.3.2 installed
Linux Machine - No ISE or EDK installed, tried both SuSE linux & Red Hat
Fedora

Get MLD files
	download edk_user_repository.zip (web page indicates March 16,
2005)
	Install on WinXP machine

Create project
	microblaze 3.00.a
	opb_mdm 2.01.a
	lmb_bram
	opb_uartlite 1.00.b
	opb_gpio 3.01.b
	opb_ddr 1.10.a
	opb_ethernet 1.02.a
	opb_emc 2.00.a
	opb_timer 1.00.b
	opb_intc 1.00.c
	
Generate auto-config.in by running Generate Libraries & BSPs

Get source (this was done on June 14, 2005)
1)	cvs -d:pserver:anonymous@cvs.uclinux.org:/var/cvs login
2)	cvs -z3 -d:pserver:anonymous@cvs.uclinux.org:/var/cvs co
uClinux-dist
3)	cvs -z3 -d:pserver:anonymous@cvs.uclinux.org:/var/cvs co
uClinux-2.4.x
4)	cd ~/uClinux-dist
5)	ln -s ../uClinux-2.4.x linux-2.4.x

Get tools
	download microblaze-elf-tools-20050308.tar.tar
	rename microblaze-elf-tools-20050308.tar.tar
microblaze-elf-tools-20050308.tar.gz
	gunzip microblaze-elf-tools-20050308.tar.gz
	tar -xf microblaze-elf-tools-20050308.tar
	add to path with export PATH=/usr/local/...:${PATH}

Copy auto-config.in to
uClinux-2.4.x/arch/microblaze/platform/uclinux-auto

Perform Build
	make menuconfig
		choose Vendor/Product Selection
			choose Xilinx,
			choose uclinux-auto
			exit
		choose Kernal/Libraries/Default
			choose Customize kernal settings
			exit
		exit
		yes to save
		CFI flash - ENTER
		Conexant - ENTER
		flashloader/ramloader - ENTER
		printbenv - ENTER
		setbenv - ENTER
		reset - ENTER
		ts_test - ENTER
		test - ENTER
		mame - ENTER
		In kernal config, exit & yes to save
	make dep
	make
		support utmp and wtmp - ENTER

Resulting error :

mb-gcc  -Os -g -fomit-frame-pointer -fno-common -Wall   -mno-xl-soft-mul
-mxl-soft-div -Dlinux -D__linux__ -Dunix -D__uClinux__ -DEMBED -nostdinc
-I/home/bkarsten/uCLinux_061405/uClinux-dist/include
-I/home/bkarsten/uCLinux_061405/uClinux-dist/include/include
-fno-builtin -Wl,-elf2flt -nostartfiles
/home/bkarsten/uCLinux_061405/uClinux-dist/lib/crt0.o
-L/home/bkarsten/uCLinux_061405/uClinux-dist/lib -o ftpd auth.o conf.o
ftpcmd.o ftpd.o popen.o server_mode.o localhost.o xgetcwd.o logwtmp.o
xmalloc.o -lcrypt_old -lc
/home/bkarsten/bin/bin/../lib/gcc-lib/microblaze/2.95.3-4/./libgcc.a
/home/bkarsten/bin/bin/../lib/gcc-lib/microblaze/2.95.3-4/./../../../../
microblaze/lib/libc_hard.a  -lc
/home/bkarsten/bin/bin/mb-ld.real: cannot find -lcrypt_old
make[2]: *** [ftpd] Error 1
make[2]: Leaving directory
`/home/bkarsten/uCLinux_061405/uClinux-dist/user/ftpd'
make[1]: *** [all] Error 2
make[1]: Leaving directory
`/home/bkarsten/uCLinux_061405/uClinux-dist/user'
make: *** [subdirs] Error 1


My auto-config.in :

############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 
# Description: uClinux Configuration File
# 
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x84000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x04000000

# FLASH_MEMORY Settings
define_hex CONFIG_XILINX_FLASH_START 0x82000000
define_hex CONFIG_XILINX_FLASH_SIZE 0x00800000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex4
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x84000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x87FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 13
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x84000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x87FFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 1
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 13
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 3.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmbcntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x07800000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmbcntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmbcntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x07800000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmbcntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# No. of instances for LMB_BRAM_IF_CNTLR
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debugmodule
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x80800000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x8080FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex4
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debugmodule
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# No. of instances for MDM
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232Uart
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x81810000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x8181FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 9600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232Uart
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 2

# No. of instances for UARTLITE
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs4Bit
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x82E00000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x82E0FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex4
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs4Bit
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# No. of instances for GPIO
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1

# Definitions for DDR_0
define_string CONFIG_XILINX_DDR_0_INSTANCE DDRSDRAM64Mx32
define_int CONFIG_XILINX_DDR_0_INCLUDE_BURST_SUPPORT 0
define_int CONFIG_XILINX_DDR_0_REG_DIMM 0
define_int CONFIG_XILINX_DDR_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_DDR_0_NUM_CLK_PAIRS 1
define_string CONFIG_XILINX_DDR_0_FAMILY virtex4
define_int CONFIG_XILINX_DDR_0_DDR_TMRD 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWR 20000
define_int CONFIG_XILINX_DDR_0_DDR_TWTR 1
define_int CONFIG_XILINX_DDR_0_DDR_TRAS 60000
define_int CONFIG_XILINX_DDR_0_DDR_TRC 90000
define_int CONFIG_XILINX_DDR_0_DDR_TRFC 80000
define_int CONFIG_XILINX_DDR_0_DDR_TRCD 30000
define_int CONFIG_XILINX_DDR_0_DDR_TRRD 15000
define_int CONFIG_XILINX_DDR_0_DDR_TREFC 70300000
define_int CONFIG_XILINX_DDR_0_DDR_TREFI 7800000
define_int CONFIG_XILINX_DDR_0_DDR_TRP 30000
define_int CONFIG_XILINX_DDR_0_DDR_CAS_LAT 2
define_int CONFIG_XILINX_DDR_0_DDR_DWIDTH 16
define_int CONFIG_XILINX_DDR_0_DDR_AWIDTH 13
define_int CONFIG_XILINX_DDR_0_DDR_COL_AWIDTH 9
define_int CONFIG_XILINX_DDR_0_DDR_BANK_AWIDTH 2
define_hex CONFIG_XILINX_DDR_0_MEM0_BASEADDR 0x84000000
define_hex CONFIG_XILINX_DDR_0_MEM0_HIGHADDR 0x87FFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_DDR_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_DDR_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_DDR_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_DDR_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_DDR_0_SIM_INIT_TIME_PS 200000000
define_string CONFIG_XILINX_DDR_0_INSTANCE DDRSDRAM64Mx32
define_string CONFIG_XILINX_DDR_0_HW_VER 1.10.a

# No. of instances for DDR
define_int CONFIG_XILINX_DDR_NUM_INSTANCES 1

# Definitions for ETHERNET_0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE EthernetMAC
define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 1
define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x83A10000
define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x83A1FFFF
define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_ETHERNET_0_FAMILY virtex4
define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 32768
define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 32768
define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE EthernetMAC
define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.02.a
define_int CONFIG_XILINX_ETHERNET_0_IRQ 1

# No. of instances for ETHERNET
define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1

# Definitions for EMC_0
define_string CONFIG_XILINX_EMC_0_INSTANCE FLASH2Mx32
define_int CONFIG_XILINX_EMC_0_NUM_BANKS_MEM 1
define_int CONFIG_XILINX_EMC_0_INCLUDE_BURST 0
define_int CONFIG_XILINX_EMC_0_INCLUDE_NEGEDGE_IOREGS 0
define_string CONFIG_XILINX_EMC_0_FAMILY virtex4
define_hex CONFIG_XILINX_EMC_0_MEM0_BASEADDR 0x82000000
define_hex CONFIG_XILINX_EMC_0_MEM0_HIGHADDR 0x827FFFFF
define_hex CONFIG_XILINX_EMC_0_MEM1_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_EMC_0_MEM1_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_EMC_0_MEM2_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_EMC_0_MEM2_HIGHADDR 0x00000000
define_hex CONFIG_XILINX_EMC_0_MEM3_BASEADDR 0xFFFFFFFF
define_hex CONFIG_XILINX_EMC_0_MEM3_HIGHADDR 0x00000000
define_int CONFIG_XILINX_EMC_0_MEM0_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MEM1_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MEM2_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MEM3_WIDTH 32
define_int CONFIG_XILINX_EMC_0_MAX_MEM_WIDTH 32
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_0 0
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_1 1
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_2 1
define_int CONFIG_XILINX_EMC_0_INCLUDE_DATAWIDTH_MATCHING_3 1
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_0 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_0 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_0 110000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_0 110000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_0 10000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_0 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_0 55000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_0 55000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_0 35000
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_1 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_1 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_1 15000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_1 15000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_1 7000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_1 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_1 15000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_1 12000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_1 0
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_2 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_2 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_2 15000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_2 15000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_2 7000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_2 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_2 15000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_2 12000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_2 0
define_int CONFIG_XILINX_EMC_0_SYNCH_MEM_3 0
define_int CONFIG_XILINX_EMC_0_SYNCH_PIPEDELAY_3 2
define_int CONFIG_XILINX_EMC_0_TCEDV_PS_MEM_3 15000
define_int CONFIG_XILINX_EMC_0_TAVDV_PS_MEM_3 15000
define_int CONFIG_XILINX_EMC_0_THZCE_PS_MEM_3 7000
define_int CONFIG_XILINX_EMC_0_THZOE_PS_MEM_3 7000
define_int CONFIG_XILINX_EMC_0_TWPS_MEM_3 15000
define_int CONFIG_XILINX_EMC_0_TWP_PS_MEM_3 12000
define_int CONFIG_XILINX_EMC_0_TLZWE_PS_MEM_3 0
define_int CONFIG_XILINX_EMC_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_EMC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_EMC_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_EMC_0_INSTANCE FLASH2Mx32
define_string CONFIG_XILINX_EMC_0_HW_VER 2.00.a

# No. of instances for EMC
define_int CONFIG_XILINX_EMC_NUM_INSTANCES 1

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opbtimer1
define_string CONFIG_XILINX_TIMER_0_FAMILY virtex4
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x81000000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x8100FFFF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opbtimer1
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# No. of instances for TIMER
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opbintc0
define_string CONFIG_XILINX_INTC_0_FAMILY virtex4
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x83400000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x8340FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000004
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000004
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000003
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opbintc0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# No. of instances for INTC
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1



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