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[microblaze-uclinux] ML310 and uclinux

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] ML310 and uclinux
From: Federico Garcia <fedeg@xxxxxx>
Date: Thu, 16 Jun 2005 20:07:01 +0200
Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx
User-agent: Mozilla Thunderbird 1.0 (Windows/20041206)
Hi

I am trying to generate the file 'autoconfig.in' for a XilinxML310 
Board, but i can't.
could anybody help me?
This is my mhs and my mss.
---MHS----------------------------------
# 
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 7.1 Build EDK_H.10.4
# Thu Jun 16 18:50:44 2005
# Target Board:  Xilinx Virtex-II Pro ML310 Evaluation Platform Rev D
# Family:     virtex2p
# Device:     xc2vp30
# Package:     ff896
# Speed Grade:     -6
# Processor: Microblaze
# System clock frequency: 100.000000 MHz
# Debug interface: On-Chip HW Debug Module
# Data Cache: 8 KB
# Instruction Cache: 2 KB
# On Chip Memory :  32 KB
# Total Off Chip Memory : 256 MB
# - DDR_SDRAM_32Mx64 = 256 MB
# 
##############################################################################


 PARAMETER VERSION = 2.1.0


 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_Clk, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_Addr, VEC = [0:12], DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr, VEC = [0:1], DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_CASn, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_CKE, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_CSn, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_RASn, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_WEn, DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_DM, VEC = [0:1], DIR = OUTPUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_DQS, VEC = [0:1], DIR = INOUT
 PORT fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin = 
fpga_0_DDR_SDRAM_32Mx64_DDR_DQ, VEC = [0:15], DIR = INOUT
 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT
 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT
 PORT fpga_0_LCD_OPTIONAL_GPIO_IO_pin = fpga_0_LCD_OPTIONAL_GPIO_IO, VEC 
= [0:11], DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_PAR = fpga_0_PCI32_BRIDGE_PAR, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_PERR_N = fpga_0_PCI32_BRIDGE_PERR_N, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_SERR_N = fpga_0_PCI32_BRIDGE_SERR_N, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_IRDY_N = fpga_0_PCI32_BRIDGE_IRDY_N, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_TRDY_N = fpga_0_PCI32_BRIDGE_TRDY_N, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_FRAME_N = fpga_0_PCI32_BRIDGE_FRAME_N, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_STOP_N = fpga_0_PCI32_BRIDGE_STOP_N, DIR = INOUT
 PORT fpga_0_PCI32_BRIDGE_DEVSEL_N = fpga_0_PCI32_BRIDGE_DEVSEL_N, DIR = 
INOUT
 PORT fpga_0_PCI32_BRIDGE_AD = fpga_0_PCI32_BRIDGE_AD, VEC = [31:0], DIR 
= INOUT
 PORT fpga_0_PCI32_BRIDGE_CBE = fpga_0_PCI32_BRIDGE_CBE, VEC = [3:0], 
DIR = INOUT
 PORT fpga_0_pci_arbiter_0_PCI_Gnt_n_pin = 
fpga_0_pci_arbiter_0_PCI_Gnt_n, VEC = [1:5], DIR = OUTPUT
 PORT fpga_0_pci_arbiter_0_PCI_Req_n_pin = 
fpga_0_pci_arbiter_0_PCI_Req_n, VEC = [1:5], DIR = INPUT
 PORT fpga_0_PCI32_BRIDGE_IDSEL = fpga_0_PCI32_BRIDGE_IDSEL, DIR = INPUT
 PORT fpga_0_ORGate_1_Res_pin = fpga_0_ORGate_1_Res, DIR = OUTPUT
 PORT fpga_0_ORGate_1_Res_1_pin = fpga_0_ORGate_1_Res, DIR = OUTPUT
 PORT fpga_0_ORGate_1_Res_2_pin = fpga_0_ORGate_1_Res, DIR = OUTPUT
 PORT fpga_0_PCI_CLK_FB = pci_feedback_s, DIR = INPUT
 PORT fpga_0_PCI_CLK_OUT0 = pci_clk_out_s, DIR = OUTPUT
 PORT fpga_0_PCI_CLK_OUT1 = pci_clk_out_s, DIR = OUTPUT
 PORT fpga_0_PCI_CLK_OUT2 = pci_clk_out_s, DIR = OUTPUT
 PORT fpga_0_PCI_CLK_OUT3 = pci_clk_out_s, DIR = OUTPUT
 PORT fpga_0_PCI_CLK_OUT4 = pci_clk_out_s, DIR = OUTPUT
 PORT fpga_0_PCI_CLK_OUT5 = pci_clk_out_s, DIR = OUTPUT
 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = INPUT
 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = OUTPUT
 PORT sys_clk_pin = dcm_clk_s, DIR = INPUT
 PORT sys_rst_pin = sys_rst_s, DIR = INPUT


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 2048
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 8192
 PARAMETER C_ICACHE_BASEADDR = 0xe0000000
 PARAMETER C_ICACHE_HIGHADDR = 0xefffffff
 PARAMETER C_ADDR_TAG_BITS = 17
 PARAMETER C_DCACHE_BASEADDR = 0xe0000000
 PARAMETER C_DCACHE_HIGHADDR = 0xefffffff
 PARAMETER C_DCACHE_ADDR_TAG = 15
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DOPB = mb_opb
 BUS_INTERFACE IOPB = mb_opb
 PORT CLK = sys_clk_s
 PORT DBG_CAPTURE = DBG_CAPTURE_s
 PORT DBG_CLK = DBG_CLK_s
 PORT DBG_REG_EN = DBG_REG_EN_s
 PORT DBG_TDI = DBG_TDI_s
 PORT DBG_TDO = DBG_TDO_s
 PORT DBG_UPDATE = DBG_UPDATE_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = mb_opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
 PORT DBG_CLK_0 = DBG_CLK_s
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
 PORT DBG_TDI_0 = DBG_TDI_s
 PORT DBG_TDO_0 = DBG_TDO_s
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT SYS_Rst = sys_rst_s
 PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00007fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 100000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT RX = fpga_0_RS232_Uart_RX
 PORT TX = fpga_0_RS232_Uart_TX
END

BEGIN opb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_32Mx64
 PARAMETER HW_VER = 1.10.a
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
 PARAMETER C_REG_DIMM = 1
 PARAMETER C_DDR_TMRD = 20000
 PARAMETER C_DDR_TWR = 20000
 PARAMETER C_DDR_TRAS = 60000
 PARAMETER C_DDR_TRC = 90000
 PARAMETER C_DDR_TRFC = 100000
 PARAMETER C_DDR_TRCD = 30000
 PARAMETER C_DDR_TRRD = 20000
 PARAMETER C_DDR_TRP = 30000
 PARAMETER C_DDR_TREFC = 70300000
 PARAMETER C_DDR_AWIDTH = 13
 PARAMETER C_DDR_COL_AWIDTH = 10
 PARAMETER C_DDR_BANK_AWIDTH = 2
 PARAMETER C_NUM_CLK_PAIRS = 2
 PARAMETER C_MEM0_BASEADDR = 0xe0000000
 PARAMETER C_MEM0_HIGHADDR = 0xefffffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT DDR_Addr = fpga_0_DDR_SDRAM_32Mx64_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr
 PORT DDR_CASn = fpga_0_DDR_SDRAM_32Mx64_DDR_CASn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_32Mx64_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_32Mx64_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_32Mx64_DDR_RASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_32Mx64_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_32Mx64_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_32Mx64_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_32Mx64_DDR_DQ
 PORT DDR_Clk = fpga_0_DDR_SDRAM_32Mx64_DDR_Clk & ddr_clk_feedback_out_s
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn & 0b0
 PORT Clk90_in = clk_90_s
 PORT Clk90_in_n = clk_90_n_s
 PORT OPB_Clk_n = sys_clk_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LCD_OPTIONAL
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 12
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT GPIO_IO = fpga_0_LCD_OPTIONAL_GPIO_IO
END

BEGIN opb_pci_arbiter
 PARAMETER INSTANCE = pci_arbiter_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_NUM_PCI_MSTRS = 6
 PARAMETER C_BASEADDR = 0x42a00000
 PARAMETER C_HIGHADDR = 0x42a0ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT PCI_Irdy_n = PCI32_BRIDGE_IRDY_I_pci_arbiter_0_PCI_Irdy_n
 PORT PCI_Frame_n = PCI32_BRIDGE_FRAME_I_pci_arbiter_0_PCI_Frame_n
 PORT PCI_Gnt_n = PCI32_BRIDGE_GNT_N_pci_arbiter_0_PCI_Gnt_n & 
fpga_0_pci_arbiter_0_PCI_Gnt_n
 PORT PCI_Req_n = PCI32_BRIDGE_REQ_N_toArb_pci_arbiter_0_PCI_Req_n & 
fpga_0_pci_arbiter_0_PCI_Req_n
 PORT PCI_Clk = pci_clk_s
 PORT PCI_Rst_n = sys_rst_s
END

BEGIN opb_pci
 PARAMETER INSTANCE = PCI32_BRIDGE
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DMA_CHAN_TYPE = 0
 PARAMETER C_FAMILY = virtex2p
 PARAMETER C_TRIG_PCI_READ_OCC_LEVEL = 9
 PARAMETER C_TRIG_PCI_DATA_XFER_OCC_LEVEL = 8
 PARAMETER C_TRIG_IPIF_READ_OCC_LEVEL = 4
 PARAMETER C_NUM_PCI_RETRIES_IN_WRITES = 250
 PARAMETER C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES = 1
 PARAMETER C_IPIFBAR_NUM = 2
 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x0
 PARAMETER C_IPIF_SPACETYPE_1 = 0
 PARAMETER C_MAX_LAT = 0x54
 PARAMETER C_MIN_GNT = 0x32
 PARAMETER C_NUM_IDSEL = 16
 PARAMETER C_DMA_LENGTH_WIDTH = 13
 PARAMETER C_INCLUDE_DEV_PENCODER = 1
 PARAMETER C_DEV_MIR_ENABLE = 1
 PARAMETER C_DEV_BLK_ID = 1
 PARAMETER C_INCLUDE_INTR_A_BUF = 0
 PARAMETER C_INCLUDE_REQ_N_BUF = 0
 PARAMETER C_BRIDGE_IDSEL_ADDR_BIT = 16
 PARAMETER C_DEVICE_ID = 0x0300
 PARAMETER C_VENDOR_ID = 0x10EE
 PARAMETER C_CLASS_CODE = 0x60000
 PARAMETER C_REV_ID = 0x01
 PARAMETER C_SUBSYSTEM_ID = 0xBEEF
 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0xB0DE
 PARAMETER C_IPIFBAR_0 = 0x20000000
 PARAMETER C_IPIF_HIGHADDR_0 = 0x3fffffff
 PARAMETER C_IPIFBAR_1 = 0xf0000000
 PARAMETER C_IPIF_HIGHADDR_1 = 0xf3ffffff
 PARAMETER C_BASEADDR = 0x42600000
 PARAMETER C_HIGHADDR = 0x4260ffff
 PARAMETER C_DMA_BASEADDR = 0x42800000
 PARAMETER C_DMA_HIGHADDR = 0x4280ffff
 BUS_INTERFACE MSOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
 PORT PAR = fpga_0_PCI32_BRIDGE_PAR
 PORT PERR_N = fpga_0_PCI32_BRIDGE_PERR_N
 PORT SERR_N = fpga_0_PCI32_BRIDGE_SERR_N
 PORT IRDY_N = fpga_0_PCI32_BRIDGE_IRDY_N
 PORT FRAME_N = fpga_0_PCI32_BRIDGE_FRAME_N
 PORT IRDY_I = PCI32_BRIDGE_IRDY_I_pci_arbiter_0_PCI_Irdy_n
 PORT FRAME_I = PCI32_BRIDGE_FRAME_I_pci_arbiter_0_PCI_Frame_n
 PORT DEVSEL_N = fpga_0_PCI32_BRIDGE_DEVSEL_N
 PORT STOP_N = fpga_0_PCI32_BRIDGE_STOP_N
 PORT TRDY_N = fpga_0_PCI32_BRIDGE_TRDY_N
 PORT GNT_N = PCI32_BRIDGE_GNT_N_pci_arbiter_0_PCI_Gnt_n
 PORT REQ_N_toArb = PCI32_BRIDGE_REQ_N_toArb_pci_arbiter_0_PCI_Req_n
 PORT AD = fpga_0_PCI32_BRIDGE_AD
 PORT CBE = fpga_0_PCI32_BRIDGE_CBE
 PORT IDSEL = fpga_0_PCI32_BRIDGE_IDSEL
 PORT PCLK = pci_clk_s
 PORT RST_N = sys_rst_s
END

BEGIN opb_timer
 PARAMETER INSTANCE = opb_timer_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 1
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT OPB_Clk = sys_clk_s
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = ORGate_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = or
 PARAMETER C_SIZE = 2
 PORT Op1 = sys_rst_s & 0b0
 PORT Res = fpga_0_ORGate_1_Res
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLKDV_BUF = TRUE
 PARAMETER C_CLKDV_DIVIDE = 3.000000
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK0 = sys_clk_s
 PORT CLKDV = pci_clk_s
 PORT CLKFB = sys_clk_s
 PORT RST = net_gnd
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK180_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = dcm_clk_s
 PORT CLK90 = clk_90_s
 PORT CLK180 = sys_clk_n_s
 PORT CLK270 = clk_90_n_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 0
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK270 = ddr_clk_90_n_s
 PORT CLK0 = dcm_2_FB
 PORT CLKFB = dcm_2_FB
 PORT RST = dcm_1_lock
 PORT LOCKED = dcm_2_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLKIN_PERIOD = 30.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLK0_BUF = TRUE
 PORT CLKIN = pci_clk_s
 PORT CLK0 = pci_clk_out_s
 PORT CLKFB = pci_feedback_s
 PORT RST = dcm_2_lock
 PORT LOCKED = dcm_3_lock
END


-----------------------------------
-------------------------------------------

 PARAMETER VERSION = 2.2.0


BEGIN OS
 PARAMETER OS_NAME = uclinux
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER stdout = RS232_Uart
 PARAMETER stdin = RS232_Uart
 PARAMETER main_memory = DDR_SDRAM_32Mx64
 PARAMETER MAIN_MEMORY_BANK = 0
 PARAMETER lmb_memory = ilmb_cntlr
 PARAMETER TARGET_DIR = c:\
END


BEGIN PROCESSOR
 PARAMETER DRIVER_NAME = cpu
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = microblaze_0
 PARAMETER COMPILER = mb-gcc
 PARAMETER ARCHIVER = mb-ar
 PARAMETER XMDSTUB_PERIPHERAL = debug_module
END


BEGIN DRIVER
 PARAMETER DRIVER_NAME = opbarb
 PARAMETER DRIVER_VER = 1.02.a
 PARAMETER HW_INSTANCE = mb_opb
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = debug_module
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dlmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = bram
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ilmb_cntlr
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = uartlite
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = RS232_Uart
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = ddr
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = DDR_SDRAM_32Mx64
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = gpio
 PARAMETER DRIVER_VER = 2.00.a
 PARAMETER HW_INSTANCE = LCD_OPTIONAL
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = pciarb
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = pci_arbiter_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = pci
 PARAMETER DRIVER_VER = 1.01.a
 PARAMETER HW_INSTANCE = PCI32_BRIDGE
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = tmrctr
 PARAMETER DRIVER_VER = 1.00.b
 PARAMETER HW_INSTANCE = opb_timer_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = ORGate_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_0
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_1
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_2
END

BEGIN DRIVER
 PARAMETER DRIVER_NAME = generic
 PARAMETER DRIVER_VER = 1.00.a
 PARAMETER HW_INSTANCE = dcm_3
END



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