mid july is to late for me I already
ahd to go back to 6.3 and will probably stay with that. This is not the
only issue i have had with 7.1. 7.1 had been nothing but headaches since
its release for us. So untill I see it stable I feel 6.3 is better
suited since it seems to actually give more reliable results.
"Greg Brown"
<greg.brown@xilinx.com> Sent by: owner-microblaze-uclinux@itee.uq.edu.au
06/22/2005 05:25 PM
Please respond to
microblaze-uclinux@itee.uq.edu.au
To
<microblaze-uclinux@itee.uq.edu.au>
cc
Subject
RE: [microblaze-uclinux]
ml403 hardware
Hello All:
The 7.1i issues are being resolved. We will be updating the www.xilinx.com/ml403
website with updated MicroBlaze and PowerPC designs that work with EDK
7.1i, SP2 and ISE 7.1i, SP3. This will all be ready in mid July. We apologize
for any inconvenience this has caused you.
-GregB
-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au]
On Behalf Of John Williams
Sent: Tuesday, June 21, 2005 6:21 PM
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] ml403 hardware
Hi Brett,
mcnernbm@notes.udayton.edu wrote:
> I am having some trouble getting my xilinx ml403 hardware to fully
> compile. The hardware is based on the ml403 reference design
for the
> microblaze with some modifications to resemble the ml401 uclinux
> harware. Attached is the edk 7.1 project I have been working
with.
> The vga, audio, and ps2 ports have been removed from the hardware
> since it is not needed. I can compile the libraried and the
uclinux
> bsp but i can not get the hardware to fully compile for the board.
> Any help would be greatly appreciated.
PAR is failing completely, complaining about unroutable signals and impossible
timing constraints.
This error mirrors something I've seen building microblaze systems for
the Insight S3-1500 board. I think there's something quite different
in how the 7.1 tools handle constraints, vs 6.3.
Looking at a reference design I received from Insight, it has a bunch of
extra constraints around the DDR interface - much more specific than anything
I saw previously. Below is an extract from the UCF - it's not quite
a recipe for you, but might provide a starting point.
Note that on the Xilinx ml401 page, they say that their microblaze reference
design requires EDK6.3 and ISE6.3 or greater. Same goes for the ml403
reference design page. Reading between the lines, I don't think it's
just a stale page - the 7.1 tools seem to be unsupported for the ML40x
reference designs. This is a shame, because there are issues with bitgen
and date2mem for the V4 devices in the 6.3 tools... so not sure what
the solution is.
Anyway, here's those constraints I was talking about, maybe they'll be
useful.
Cheers,
John
# Create separate timing groups based off each clock domain
NET sys_clk_s TNM = CLK0_GRP_ALL ;
NET clk_90_s TNM = CLK90_GRP_ALL ;
NET sys_clk_n_s TNM = CLK180_GRP_ALL ; NET clk_90_n_s
TNM = CLK270_GRP_ALL ;
# clk0 & clk_90 contain both rising and falling clock edges. Therefore
# break the clk0 group (CLK0_GRP_DDR) into two timing groups -- required
# to constrain each group separately.
TIMEGRP CLK0_GRP = RISING CLK0_GRP_ALL
; # clk0 registers
TIMEGRP CLK0n_GRP = FALLING CLK0_GRP_ALL ; #
clk0 registers
TIMEGRP CLK180_GRP = RISING CLK180_GRP_ALL ; #
~clk0 registers
TIMEGRP CLK90_GRP = RISING CLK90_GRP_ALL ; #
clk90 registers
TIMEGRP CLK270_GRP = RISING CLK270_GRP_ALL ; #
~clk90 registers
# Create separate timing groups based off each clock domain NET ddr_clk_90_s
TNM = DDR_CLK90_GRP_ALL; NET ddr_clk_90_n_s TNM = DDR_CLK270_GRP_ALL;
TIMEGRP DDR_CLK90_GRP = RISING DDR_CLK90_GRP_ALL ; # ddr_clk90
registers TIMEGRP DDR_CLK270_GRP = RISING DDR_CLK270_GRP_ALL ; # ~ddr_clk90
registers
# Now that all groups are created, generate the OFFSET constraints.
# Recall that the OFFSET constraints must be manually adjusted to # account
for the clock phase.
OFFSET = IN -0.75 ns VALID 5.16 ns BEFORE fpga_0_DDR_CLK_FB TIMEGRP DDR_CLK90_GRP
; # ¼ clock cycle - 0.75 ns - ¼ clock cycle, valid ½ clock cycle - DDR
Tac uncertainty OFFSET = IN -7.146 ns VALID 5.16 ns BEFORE fpga_0_DDR_CLK_FB
TIMEGRP DDR_CLK270_GRP ; # ¼ clock cycle - 0.75 ns - ¼ - ½ clock cycle,
valid ½ clock cycle - DDR Tac uncertainty
TIMESPEC TS_IGNORE03 = FROM DDR_CLK90_GRP_ALL TO CLK0_GRP_ALL
TIG; TIMESPEC TS_IGNORE04 = FROM DDR_CLK270_GRP_ALL TO CLK0_GRP_ALL
TIG;
TIMESPEC TSCLK2CLK90 = FROM CLK0_GRP_ALL TO CLK90_GRP_ALL
3.333 ns;
TIMESPEC TS_IGNORE13 = FROM DDR_CLK90_GRP_ALL TO CLK90_GRP_ALL
TIG; TIMESPEC TS_IGNORE14 = FROM DDR_CLK270_GRP_ALL TO CLK90_GRP_ALL
TIG;
TIMESPEC TS_IGNORE23 = FROM DDR_CLK90_GRP_ALL TO CLK180_GRP_ALL
TIG; TIMESPEC TS_IGNORE24 = FROM DDR_CLK270_GRP_ALL TO CLK180_GRP_ALL
TIG;
TIMESPEC TS_IGNORE33 = FROM DDR_CLK90_GRP_ALL TO CLK270_GRP_ALL
TIG; TIMESPEC TS_IGNORE34 = FROM DDR_CLK270_GRP_ALL TO CLK270_GRP_ALL
TIG;
TIMESPEC TS_IGNORE40 = FROM CLK0_GRP_ALL TO DDR_CLK90_GRP_ALL
TIG;
TIMESPEC TS_IGNORE41 = FROM CLK90_GRP_ALL TO DDR_CLK90_GRP_ALL
TIG;
TIMESPEC TS_IGNORE42 = FROM CLK180_GRP_ALL TO DDR_CLK90_GRP_ALL
TIG;
TIMESPEC TS_IGNORE43 = FROM CLK270_GRP_ALL TO DDR_CLK90_GRP_ALL
TIG;
TIMESPEC TS_IGNORE45 = FROM CLK0n_GRP TO
DDR_CLK90_GRP_ALL TIG;
TIMESPEC TS_IGNORE50 = FROM CLK0_GRP_ALL TO DDR_CLK270_GRP_ALL
TIG;
TIMESPEC TS_IGNORE51 = FROM CLK90_GRP_ALL TO DDR_CLK270_GRP_ALL
TIG;
TIMESPEC TS_IGNORE52 = FROM CLK180_GRP_ALL TO DDR_CLK270_GRP_ALL
TIG;
TIMESPEC TS_IGNORE53 = FROM CLK270_GRP_ALL TO DDR_CLK270_GRP_ALL
TIG;
TIMESPEC TS_IGNORE55 = FROM CLK0n_GRP TO
DDR_CLK270_GRP_ALL TIG;
TIMESPEC TS_IGNORE63 = FROM CLK0_GRP_ALL TO CLK0n_GRP
TIG;
TIMESPEC TS_IGNORE64 = FROM DDR_CLK90_GRP_ALL TO CLK0n_GRP
TIG; TIMESPEC TS_IGNORE65 = FROM DDR_CLK270_GRP_ALL TO CLK0n_GRP
TIG;
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