Hi folks, I've eventually succeeded in building uClinux for the spartan 3 (xc3s400) using the auto-config.in mechanism - thanks to John and previous posts to the mailing list! I'm now trying to get it to run on the board by downloading the image.elf via XMD (this takes about 20 minutes!). The download works correctly as far as I can see but the kernel hangs quite soon after start up. Below are the steps I've gone through and the output captured from the terminal. Here is the cygwin session: $ xmd Xilinx Microprocessor Debug (XMD) Engine Xilinx EDK 6.3 Build EDK_Gmm.10 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. XMD% connect mb mdm Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 6.0.3.0. LPT base address = 0378h. ECP base address = 0778h. ECP hardware is detected. Cable connection established. Connecting to cable (Parallel Port - LPT1) in ECP mode. Checking cable driver. Driver xpc4drvr.sys version = 1.0.3.0. LPT base address = 0378h. Cable Type = 1, Revision = 3. Cable connection established. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 05045093 8 XCF02S 2 0141c093 6 XC3S400 Assuming, Device No: 2 contains the MicroBlaze system Connected to the JTAG MicroBlaze Debug Module (MDM) No of processors = 1 MicroBlaze Processor 1 Configuration : ------------------------------------- Version............................3.00.a No of PC Breakpoints...............2 No of Read Addr/Data Watchpoints...1 No of Write Addr/Data Watchpoints..1 Instruction Cache Support..........off Data Cache Support.................off JTAG MDM Connected to MicroBlaze 1 Connected to "mb" target. id = 0 Starting GDB server for "mb" target (id = 0) at TCP port no 1234 XMD% XMD% XMD% XMD% xload mhs system.mhs Loading MHS File.. Processor(s) in System :: Microblaze(1) : microblaze_0 Address Map for Processor microblaze_0 (0x00000000-0x00001fff) dlmb_cntlr dlmb (0x00000000-0x00001fff) ilmb_cntlr ilmb (0x81000000-0x810000ff) opb_timer_1 mb_opb (0x81000100-0x810001ff) opb_intc_0 mb_opb (0x81000200-0x810002ff) debug_module mb_opb (0x81000300-0x810003ff) USB_UART mb_opb (0x81000400-0x810005ff) SRAM_256Kx32_FLASH_2Mx32 mb_opb (0x81000600-0x810006ff) RS232 mb_opb (0x81000800-0x810009ff) LED_7Segment mb_opb (0x81004000-0x81007fff) Ethernet_MAC mb_opb (0x81100000-0x811fffff) SRAM_256Kx32_FLASH_2Mx32 mb_opb (0x81800000-0x81ffffff) SRAM_256Kx32_FLASH_2Mx32 mb_opb XMD% XMD% XMD% dow images/image.elf section, .text: 0x81100000-0x811b7f68 section, .intv: 0x811b7f68-0x811b7fa0 section, .init: 0x811c3000-0x811cd000 Checking if Program I-Side Memory within Address Range....PASSED $ section, .sdata2: 0x811b7fa0-0x811b9550 section, .data: 0x811b9550-0x811c2020 section, .bss: 0x811cd000-0x811ebc24 section, .romfs: 0x811cd000-0x811d0c00 Checking if Program D-Side Memory within Address Range....PASSED Downloaded Program images/image.elf Setting PC with program start addr = 0x81100000 XMD% con Processor started. Type "stop" to stop processor RUNNING> And here is the output I see at the serial port.. Linux version 2.4.29-uc1 (vinc@shn-linux1.corp.avocent.com) (gcc version 2.95.3-4 Xilinx EDK 6.3 Build EDK_Gmm.12.2) #32 Wed Jun 22 14:42:03 IST 2005 On node 0 totalpages: 256 zone(0): 256 pages. BUG: wrong zone alignment, it will crash zone(1): 0 pages. zone(2): 0 pages. CPU: MICROBLAZE Kernel command line: ¸ Console: xmbserial on UARTLite Calibrating delay loop... 3.72 BogoMIPS Memory: 1MB = 1MB total Memory: 64KB available (735K code, 207K data, 40K init) kernel BUG at slab.c:1013! Has anybody seen this type of error before? Any idea's as to what may be incorrectly configured? I've attached the autoconfig.in file. Thanks in advance, Vincent -----Original Message----- From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of John Williams Sent: 20 June 2005 13:06 To: microblaze-uclinux@itee.uq.edu.au Subject: Re: [microblaze-uclinux] auto-config, Spartan 3 (xc3s400) Carr, Vincent wrote: > Here are the fragments from the MHS and MSS file. I've attached > complete files also. > > PARAMETER main_memory = SRAM_256Kx32_FLASH_2Mx32 > PARAMETER flash_memory = SRAM_256Kx32_FLASH_2Mx32 OK, so you need to provide the *_BANK options here as well, e.g. PARAMETER main_memory_bank = 0 PARAMETER flash_memory_bank = 1 to tell the BSP which of the banks on that controller corresponds to the main and flash memories respectively. Cheers, John ___________________________ microblaze-uclinux mailing list microblaze-uclinux@itee.uq.edu.au Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
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