RE: [microblaze-uclinux] Avnet XCS2000 S3 boot complete

["Errol Terblanche" <rince@xxxxxxxxxxx>]

I have been thinking about this slab.c thing this morning and if my problem
was limited to MB 4.00. 

I'm using MB 4.00 and ISE 7.1 and I have to disable the 32KB cache in the
list of caches that gets created in slab.c:


***snip***
#ifndef CONFIG_CONTIGUOUS_PAGE_ALLOC /* assumes page size of 4096 */
	{  8192,	NULL, NULL},
	{ 16384,	NULL, NULL},
//	{ 32768,	NULL, NULL},
	{ 65536,	NULL, NULL},
	{131072,	NULL, NULL},
***snip***

I have yet to confirm if this is a problem on my side, or in MB 4.00. For
some reason it tries to create a 4GB cache instead of the 32KB, all other
caches creates fine...

I'm only using hardware multiply...

Thanx,
Errol





-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au
[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of
alucero@os3sl.com
Sent: Friday, June 24, 2005 9:31 PM
To: microblaze-uclinux@itee.uq.edu.au
Subject: [microblaze-uclinux] Avnet XCS2000 S3 boot complete

Hi,

I'm happiest man in the world !  (At least at this exactly moment)

I have had some problems, and the boot is succesful but with several 
limitations:

1) Using msrcrl & msrset instructions the boot stalls at calibrate_delay. 
After some tests I discovered that msrclr was not working in the right way 
and the flags stored were 0x0. I have disabled these functions in the mhs 
file (and recompiled the kernel with the new autoconfig) and things were 
getting better but ...

2) I dont know why but BIP bit (MSR) was actived at the beginning of 
calibration_delay, so I'm disabling the bit (hardcoded) inside this
function.
Can someone tell me why this bit is on?

3) Once calibration delay was left behind, the boot stalls at slab.c (682). 
However, I had discovered before that this does not happen with Microblaze 
3.00. So I changed the mhs file from 4.00 to 3.00. 

And login appered !!!

Before this moment, I thought that I could have something wrong in my
hardware 
configuration, since I'm far to be a FPGA programmer expert (this is my
first 
experience with this wonderful world), but as now this is working I suppose 
my conf in OK. As I know there are people working with msrclr & msrset and 
with Microblaze 4.00, the question is: are you using ISE 7.1?

I try to get a reason for my configuration limitations.



-- 
Alejandro Lucero
OS3, OS Serveis i Solucions
www.os3sl.com
Ingeniería Informática
+34 665687168
Av.Benjamin Franklin
CEEI. Parque Tecnológico de Paterna
Valencia(Spain)

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