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[microblaze-uclinux] Kernel panic: VFS: Unable to mount root fs on 1f:00

To: microblaze-uclinux@xxxxxxxxxxxxxx
Subject: [microblaze-uclinux] Kernel panic: VFS: Unable to mount root fs on 1f:00
From: Anuroop M <anuroop.m@xxxxxxxxx>
Date: Thu, 21 Jul 2005 18:58:02 +0530
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Reply-to: microblaze-uclinux@xxxxxxxxxxxxxx
Sender: owner-microblaze-uclinux@xxxxxxxxxxxxxx

Hi john,
I am facing serous problem with mounting the file system. Is it possible to mount the file system to ramdisk ?, without using a ROM?.
I have edited the file according to the article on the net . http://www.ucdot.org/article.pl?sid=03/01/11/1049210&mode=thread

but the ram probe size is some junk.

uclinux[mtd]: RAM probe address=0x86126098 size= 0x15ee6000
but my ram is only 32mb and its 0x86000000 to 0x87FFFFFF

.
but i don't understand why the size is different.

i had attached the auto-config.in with this mail.

i don't understand what is the problem with this??.. whether it is because of any kernel configuration that i missed... ??
please help..

boot log is given below.

-------------------------------------------------------------------------------------------------------------------
Linux version 2.4.29-uc1 (root@jithin1.core.com) (gcc version 2.95.3-4 Xilinx E
DK 6.3 Build EDK_Gmm.12.2) #216 Wed Jul 20 16:41:13 IST 2005
On node 0 totalpages: 8192
zone(0): 8192 pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Kernel command line:
Console: xmbserial on UARTLite
Calibrating delay loop... 4.00 BogoMIPS
Memory: 32MB = 32MB total
Memory: 31236KB available (954K code, 214K data, 44K init)
Dentry cache hash table entries: 4096 (order: 3, 32768 bytes)
Inode cache hash table entries: 2048 (order: 2, 16384 bytes)
Mount cache hash table entries: 512 (order: 0, 4096 bytes)

SB nodev flags = 0,name =rootfs
assigning mnt_sb = sb
retval mnt = -2044735212
***************
SB nodev flags = 0,name =bdev
assigning mnt_sb = sb
retval mnt = -2044735152
***************<6>Buffer cache hash table entries: 1024 (order: 0, 4096 bytes)
Page-cache hash table entries: 8192 (order: 3, 32768 bytes)

SB FS_SINGLE flags = 0,name =proc
assigning mnt_sb = sb
retval mnt = -2044735092
***************POSIX conformance testing by UNIFIX
Linux NET4.0 for Linux 2.4
Based upon Swansea University Computer Society NET3.039

SB nodev flags = 0,name =sockfs
assigning mnt_sb = sb
retval mnt = -2044735032
***************Initializing RT netlink socket
Microblaze UARTlite serial driver version 1.00
ttyS0 at 0x84020000 (irq = 1) is a Microblaze UARTlite
Starting kswapd

SB nodev flags = 0,name =pipefs
assigning mnt_sb = sb
retval mnt = -2044734972
***************<6>xgpio #0 at 0x84030000 mapped to 0x84030000
Xilinx GPIO registered
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
eth0: using fifo mode.
eth0: Xilinx EMAC #0 at 0x84040000 mapped to 0x84040000, irq=2
eth0: id 2.0h; block id 7, type 1
uclinux[mtd]: RAM probe address=0x86124098 size=0x15ee6000
uclinux[mtd]: root filesystem index=0
slram: not enough parameters.
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 2048 bind 2048)
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
*******
VFS: test name = </dev/root>
VFS: fs_name = <ext2>
VFS: root name <1f:00>
*******
VFS: tried fs_name = <ext2> err= -22
Kernel panic: VFS: Unable to mount root fs on 1f:00

-------------------------------------------------------------------------------------------------------------------

It will be a great help for me ..
Thanks in advance
--Anuroop

############################################################
# 
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3 
# Description: uClinux Configuration File
# 
############################################################



# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x86000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x02000000

# LMB_MEMORY Settings
define_hex CONFIG_XILINX_LMB_START 0x00000000
define_hex CONFIG_XILINX_LMB_SIZE 0x00002000

# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 100000000

# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY virtex2p
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 17
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 17
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 8192
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 3.00.a

# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x04000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b

# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x04000000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b

# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x84010000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x8401FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY virtex2p
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 8
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE debug_module
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a

# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x84020000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x8402FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 100000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 57600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 1

# Definitions for ETHERNET_0
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_int CONFIG_XILINX_ETHERNET_0_DEV_BLK_ID 1
define_int CONFIG_XILINX_ETHERNET_0_DEV_MIR_ENABLE 1
define_hex CONFIG_XILINX_ETHERNET_0_BASEADDR 0x84040000
define_hex CONFIG_XILINX_ETHERNET_0_HIGHADDR 0x8404FFFF
define_int CONFIG_XILINX_ETHERNET_0_RESET_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_INCLUDE_DEV_PENCODER 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_PRESENT 1
define_int CONFIG_XILINX_ETHERNET_0_DMA_INTR_COALESCE 1
define_int CONFIG_XILINX_ETHERNET_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_ETHERNET_0_OPB_CLK_PERIOD_PS 10000
define_string CONFIG_XILINX_ETHERNET_0_FAMILY virtex2p
define_int CONFIG_XILINX_ETHERNET_0_IPIF_RDFIFO_DEPTH 32768
define_int CONFIG_XILINX_ETHERNET_0_IPIF_WRFIFO_DEPTH 32768
define_hex CONFIG_XILINX_ETHERNET_0_MIIM_CLKDVD 0x0000001F
define_int CONFIG_XILINX_ETHERNET_0_SOURCE_ADDR_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_PAD_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_FCS_INSERT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_DEPTH 64
define_int CONFIG_XILINX_ETHERNET_0_MAFIFO_BRAM_1_SRL_0 0
define_int CONFIG_XILINX_ETHERNET_0_HALF_DUPLEX_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_ERR_COUNT_EXIST 1
define_int CONFIG_XILINX_ETHERNET_0_CAM_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_CAM_BRAM_0_SRL_1 1
define_int CONFIG_XILINX_ETHERNET_0_JUMBO_EXIST 0
define_int CONFIG_XILINX_ETHERNET_0_MII_EXIST 1
define_string CONFIG_XILINX_ETHERNET_0_INSTANCE Ethernet_MAC
define_string CONFIG_XILINX_ETHERNET_0_HW_VER 1.02.a
define_int CONFIG_XILINX_ETHERNET_0_IRQ 2

# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x84030000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x8403FFFF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY virtex2p
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 4
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE LEDs_4Bit
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b

# Definitions for SDRAM_0
define_string CONFIG_XILINX_SDRAM_0_INSTANCE SDRAM_8Mx32
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_BURST_SUPPORT 1
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_HIGHSPEED_PIPE 0
define_int CONFIG_XILINX_SDRAM_0_USE_POSEDGE_OUTREGS 0
define_string CONFIG_XILINX_SDRAM_0_FAMILY virtex2p
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TMRD 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TWR 15000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TCCD 1
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRAS 48000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRC 70000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRFC 75000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRCD 19000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRRD 16000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRP 19000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREF 64
define_int CONFIG_XILINX_SDRAM_0_SDRAM_REFRESH_NUMROWS 8192
define_int CONFIG_XILINX_SDRAM_0_SDRAM_CAS_LAT 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_DWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_SDRAM_AWIDTH 12
define_int CONFIG_XILINX_SDRAM_0_SDRAM_COL_AWIDTH 9
define_int CONFIG_XILINX_SDRAM_0_SDRAM_BANK_AWIDTH 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREFI 7812500
define_hex CONFIG_XILINX_SDRAM_0_BASEADDR 0x86000000
define_hex CONFIG_XILINX_SDRAM_0_HIGHADDR 0x87FFFFFF
define_int CONFIG_XILINX_SDRAM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_CLK_PERIOD_PS 10000
define_int CONFIG_XILINX_SDRAM_0_SIM_INIT_TIME_PS 100000000
define_string CONFIG_XILINX_SDRAM_0_INSTANCE SDRAM_8Mx32
define_string CONFIG_XILINX_SDRAM_0_HW_VER 1.00.e

# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY virtex2p
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x84000000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x8400FFFF
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 3
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000002
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000002
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000005
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c

# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_0
define_string CONFIG_XILINX_TIMER_0_FAMILY virtex2p
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0xFFFF1000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0xFFFF10FF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_0
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 0

# Peripheral counts
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_SDRAM_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1
define_int CONFIG_XILINX_ETHERNET_NUM_INSTANCES 1

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