RE: [microblaze-uclinux] Power Management?

["Errol Terblanche" <rince@xxxxxxxxxxx>]

Hi John,

I'm using a MT48LC32M8A2 by Micron, but their whole 256Mb range has same
features, and probably their other DRAMs as well...

This is a snip from the datasheet:
<snip>
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking.
<snip>

The DRAM has a ClockEnable pin, if that is taken low then the DRAM enters
this self refresh mode...

Also, the DRAM's spec quotes 2.5mA for the standard device and 1.5mA for the
low power device in self refresh mode...

Of course this will require a much more complex boot loader to check if it
is a power up, or a resume in which case it must restore the stack and CPU
registers. 

Thanx,
Errol



-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au
[mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of John Williams
Sent: Friday, July 29, 2005 6:36 AM
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] Power Management?

Hi Errol,

Errol Terblanche wrote:

> Just for interest's sake, has anybody looked at power management? I have 
> seen speculation about clock management, but I'm more interested in 
> Suspend To Ram to power-off the whole board except DRAM.
> 
> I'm busy designing a custom board and I'm wondering if I should add the 
> possibility to power down things like the VCCint and VCCaux (even 
> VCCio?) to facilitate STR.
> 
> Any thoughts on this?

I might be missing something here, but presumably the DRAM controller is 
implemented in the FPGA, and so powering it down would stop the needed 
refresh cycles on the DRAM?

Is there such a thing as self-refreshing DRAM?  Or maybe you could put 
the DRAM controller in a CPLD, and interface that to the FPGA, and, 
and...  seems to get complicated pretty quickly.

Cheers,

John
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