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[microblaze-uclinux] StarterKit+uClinux beginer
Hi, sorry for my poor English.
I have Xilinx StarterKit (Spartan3-200 rev E) and I want run uClinux on this
board.
First step I connect external SDRAM (16Mx16) from onboard connectors (work
correctly, I tested).
Next I download uClinux distributives from www.uclinux.org and packages from
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/.
Next I generate "auto-config.in" file and compile uClinux image.
Next I download image thought XMD to SDRAM and run it.
But booting process stopped in "Calibrate delay loop :" :(
Booting screen:
Linux version 2.4.27-uc1 (root@localhost) (gcc version 2.95.3-4 Xilinx EDK
6.3 Build EDK_Gmm.12.2) #22 ?'N??? ????? 7 22:14:45 SAMST 2005
On node 0 totalpages: 8192
zone(0): 8192 pages.
zone(1): 0 pages.
zone(2): 0 pages.
CPU: MICROBLAZE
Console: xmbserial on UARTLite
Kernel command line:
Calibrating delay loop...
auto-config.in file:
############################################################
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 7.1.1 EDK_H.11.3
# Description: uClinux Configuration File
#
############################################################
# MAIN_MEMORY Settings
define_hex CONFIG_XILINX_ERAM_START 0x86000000
define_hex CONFIG_XILINX_ERAM_SIZE 0x02000000
# System Clock Frequency
define_int CONFIG_XILINX_CPU_CLOCK_FREQ 50000000
# Definitions for MICROBLAZE0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_FAMILY spartan3
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_int CONFIG_XILINX_MICROBLAZE0_D_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_D_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_OPB 1
define_int CONFIG_XILINX_MICROBLAZE0_I_LMB 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_BARREL 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_DIV 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL 1
define_int CONFIG_XILINX_MICROBLAZE0_USE_FPU 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR 0
define_int CONFIG_XILINX_MICROBLAZE0_UNALIGNED_EXCEPTIONS 0
define_int CONFIG_XILINX_MICROBLAZE0_ILL_OPCODE_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_IOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DOPB_BUS_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DIV_ZERO_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_FPU_EXCEPTION 0
define_int CONFIG_XILINX_MICROBLAZE0_DEBUG_ENABLED 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_PBRK 2
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_RD_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_NUMBER_OF_WR_ADDR_BRK 1
define_int CONFIG_XILINX_MICROBLAZE0_INTERRUPT_IS_EDGE 0
define_int CONFIG_XILINX_MICROBLAZE0_EDGE_IS_POSITIVE 1
define_int CONFIG_XILINX_MICROBLAZE0_FSL_LINKS 0
define_int CONFIG_XILINX_MICROBLAZE0_FSL_DATA_SIZE 32
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_ICACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_ICACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_ICACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_ADDR_TAG_BITS 18
define_int CONFIG_XILINX_MICROBLAZE0_CACHE_BYTE_SIZE 4096
define_int CONFIG_XILINX_MICROBLAZE0_ICACHE_USE_FSL 0
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_BASEADDR 0x00000000
define_hex CONFIG_XILINX_MICROBLAZE0_DCACHE_HIGHADDR 0x3FFFFFFF
define_int CONFIG_XILINX_MICROBLAZE0_USE_DCACHE 0
define_int CONFIG_XILINX_MICROBLAZE0_ALLOW_DCACHE_WR 1
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_ADDR_TAG 18
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_BYTE_SIZE 4096
define_int CONFIG_XILINX_MICROBLAZE0_DCACHE_USE_FSL 0
define_string CONFIG_XILINX_MICROBLAZE0_INSTANCE microblaze_0
define_string CONFIG_XILINX_MICROBLAZE0_HW_VER 4.00.a
# Definitions for LMB_BRAM_IF_CNTLR_0
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_MASK 0x07200000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_INSTANCE dlmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_0_HW_VER 1.00.b
# Definitions for LMB_BRAM_IF_CNTLR_1
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_BASEADDR 0x00000000
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HIGHADDR 0x00001FFF
define_hex CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_MASK 0x07200000
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_AWIDTH 32
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_LMB_DWIDTH 32
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_INSTANCE ilmb_cntlr
define_string CONFIG_XILINX_LMB_BRAM_IF_CNTLR_1_HW_VER 1.00.b
# Definitions for UARTLITE_0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_hex CONFIG_XILINX_UARTLITE_0_BASEADDR 0x20600000
define_hex CONFIG_XILINX_UARTLITE_0_HIGHADDR 0x2060FFFF
define_int CONFIG_XILINX_UARTLITE_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_UARTLITE_0_DATA_BITS 8
define_int CONFIG_XILINX_UARTLITE_0_CLK_FREQ 50000000
define_int CONFIG_XILINX_UARTLITE_0_BAUDRATE 57600
define_int CONFIG_XILINX_UARTLITE_0_USE_PARITY 0
define_int CONFIG_XILINX_UARTLITE_0_ODD_PARITY 0
define_string CONFIG_XILINX_UARTLITE_0_INSTANCE RS232
define_string CONFIG_XILINX_UARTLITE_0_HW_VER 1.00.b
define_int CONFIG_XILINX_UARTLITE_0_IRQ 0
# Definitions for MDM_0
define_string CONFIG_XILINX_MDM_0_INSTANCE opb_mdm_0
define_hex CONFIG_XILINX_MDM_0_BASEADDR 0x32000000
define_hex CONFIG_XILINX_MDM_0_HIGHADDR 0x3200FFFF
define_int CONFIG_XILINX_MDM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_MDM_0_OPB_AWIDTH 32
define_string CONFIG_XILINX_MDM_0_FAMILY spartan3
define_int CONFIG_XILINX_MDM_0_MB_DBG_PORTS 1
define_int CONFIG_XILINX_MDM_0_USE_UART 1
define_int CONFIG_XILINX_MDM_0_UART_WIDTH 32
define_int CONFIG_XILINX_MDM_0_WRITE_FSL_PORTS 0
define_string CONFIG_XILINX_MDM_0_INSTANCE opb_mdm_0
define_string CONFIG_XILINX_MDM_0_HW_VER 2.00.a
# Definitions for SDRAM_0
define_string CONFIG_XILINX_SDRAM_0_INSTANCE opb_sdram_0
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_BURST_SUPPORT 1
define_int CONFIG_XILINX_SDRAM_0_INCLUDE_HIGHSPEED_PIPE 1
define_int CONFIG_XILINX_SDRAM_0_USE_POSEDGE_OUTREGS 0
define_string CONFIG_XILINX_SDRAM_0_FAMILY spartan3
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TMRD 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TWR 15000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TCCD 1
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRAS 120000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRC 70000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRFC 75000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRCD 20000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRRD 15000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TRP 20000
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREF 64
define_int CONFIG_XILINX_SDRAM_0_SDRAM_REFRESH_NUMROWS 8192
define_int CONFIG_XILINX_SDRAM_0_SDRAM_CAS_LAT 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_DWIDTH 16
define_int CONFIG_XILINX_SDRAM_0_SDRAM_AWIDTH 13
define_int CONFIG_XILINX_SDRAM_0_SDRAM_COL_AWIDTH 9
define_int CONFIG_XILINX_SDRAM_0_SDRAM_BANK_AWIDTH 2
define_int CONFIG_XILINX_SDRAM_0_SDRAM_TREFI 7812500
define_hex CONFIG_XILINX_SDRAM_0_BASEADDR 0x86000000
define_hex CONFIG_XILINX_SDRAM_0_HIGHADDR 0x87FFFFFF
define_int CONFIG_XILINX_SDRAM_0_OPB_DWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_SDRAM_0_OPB_CLK_PERIOD_PS 20000
define_int CONFIG_XILINX_SDRAM_0_SIM_INIT_TIME_PS 100000000
define_string CONFIG_XILINX_SDRAM_0_INSTANCE opb_sdram_0
define_string CONFIG_XILINX_SDRAM_0_HW_VER 1.00.e
# Definitions for GPIO_0
define_string CONFIG_XILINX_GPIO_0_INSTANCE opb_gpio_0
define_hex CONFIG_XILINX_GPIO_0_BASEADDR 0x31000000
define_hex CONFIG_XILINX_GPIO_0_HIGHADDR 0x310001FF
define_int CONFIG_XILINX_GPIO_0_USER_ID_CODE 3
define_int CONFIG_XILINX_GPIO_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_GPIO_0_OPB_DWIDTH 32
define_string CONFIG_XILINX_GPIO_0_FAMILY spartan3
define_int CONFIG_XILINX_GPIO_0_GPIO_WIDTH 2
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS 0
define_int CONFIG_XILINX_GPIO_0_INTERRUPT_PRESENT 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR 0
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT 0xFFFFFFFF
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT 0xFFFFFFFF
define_int CONFIG_XILINX_GPIO_0_IS_DUAL 0
define_int CONFIG_XILINX_GPIO_0_ALL_INPUTS_2 0
define_int CONFIG_XILINX_GPIO_0_IS_BIDIR_2 1
define_hex CONFIG_XILINX_GPIO_0_DOUT_DEFAULT_2 0x00000000
define_hex CONFIG_XILINX_GPIO_0_TRI_DEFAULT_2 0xFFFFFFFF
define_string CONFIG_XILINX_GPIO_0_INSTANCE opb_gpio_0
define_string CONFIG_XILINX_GPIO_0_HW_VER 3.01.b
# Definitions for TIMER_0
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_0
define_string CONFIG_XILINX_TIMER_0_FAMILY spartan3
define_int CONFIG_XILINX_TIMER_0_COUNT_WIDTH 32
define_int CONFIG_XILINX_TIMER_0_ONE_TIMER_ONLY 0
define_int CONFIG_XILINX_TIMER_0_TRIG0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_TRIG1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN0_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_GEN1_ASSERT 1
define_int CONFIG_XILINX_TIMER_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_TIMER_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_TIMER_0_BASEADDR 0x33000000
define_hex CONFIG_XILINX_TIMER_0_HIGHADDR 0x330000FF
define_string CONFIG_XILINX_TIMER_0_INSTANCE opb_timer_0
define_string CONFIG_XILINX_TIMER_0_HW_VER 1.00.b
define_int CONFIG_XILINX_TIMER_0_IRQ 1
# Definitions for INTC_0
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_FAMILY spartan3
define_int CONFIG_XILINX_INTC_0_Y 0
define_int CONFIG_XILINX_INTC_0_X 0
define_string CONFIG_XILINX_INTC_0_U_SET intc
define_int CONFIG_XILINX_INTC_0_OPB_AWIDTH 32
define_int CONFIG_XILINX_INTC_0_OPB_DWIDTH 32
define_hex CONFIG_XILINX_INTC_0_BASEADDR 0x34000000
define_hex CONFIG_XILINX_INTC_0_HIGHADDR 0x3400001F
define_int CONFIG_XILINX_INTC_0_NUM_INTR_INPUTS 2
define_hex CONFIG_XILINX_INTC_0_KIND_OF_INTR 0x00000001
define_hex CONFIG_XILINX_INTC_0_KIND_OF_EDGE 0x00000001
define_hex CONFIG_XILINX_INTC_0_KIND_OF_LVL 0x00000002
define_int CONFIG_XILINX_INTC_0_HAS_IPR 1
define_int CONFIG_XILINX_INTC_0_HAS_SIE 1
define_int CONFIG_XILINX_INTC_0_HAS_CIE 1
define_int CONFIG_XILINX_INTC_0_HAS_IVR 1
define_int CONFIG_XILINX_INTC_0_IRQ_IS_LEVEL 1
define_int CONFIG_XILINX_INTC_0_IRQ_ACTIVE 1
define_string CONFIG_XILINX_INTC_0_INSTANCE opb_intc_0
define_string CONFIG_XILINX_INTC_0_HW_VER 1.00.c
# Peripheral counts
define_int CONFIG_XILINX_LMB_BRAM_IF_CNTLR_NUM_INSTANCES 2
define_int CONFIG_XILINX_TIMER_NUM_INSTANCES 1
define_int CONFIG_XILINX_INTC_NUM_INSTANCES 1
define_int CONFIG_XILINX_MDM_NUM_INSTANCES 1
define_int CONFIG_XILINX_UARTLITE_NUM_INSTANCES 1
define_int CONFIG_XILINX_GPIO_NUM_INSTANCES 1
define_int CONFIG_XILINX_SDRAM_NUM_INSTANCES 1
MHS file:
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPUT
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPUT
PORT sys_clk_pin = dcm_clk_s, DIR = INPUT
PORT sys_rst_pin = sys_rst_s, DIR = INPUT
PORT opb_sdram_0_SDRAM_Clk = opb_sdram_0_SDRAM_Clk, DIR = O
PORT opb_sdram_0_SDRAM_CKE = opb_sdram_0_SDRAM_CKE, DIR = O
PORT opb_sdram_0_SDRAM_CSn = opb_sdram_0_SDRAM_CSn, DIR = O
PORT opb_sdram_0_SDRAM_RASn = opb_sdram_0_SDRAM_RASn, DIR = O
PORT opb_sdram_0_SDRAM_CASn = opb_sdram_0_SDRAM_CASn, DIR = O
PORT opb_sdram_0_SDRAM_WEn = opb_sdram_0_SDRAM_WEn, DIR = O
PORT opb_sdram_0_SDRAM_DQM = opb_sdram_0_SDRAM_DQM, VEC = [0:1], DIR = O
PORT opb_sdram_0_SDRAM_BankAddr = opb_sdram_0_SDRAM_BankAddr, VEC = [0:1],
DIR = O
PORT opb_sdram_0_SDRAM_Addr = opb_sdram_0_SDRAM_Addr, VEC = [0:12], DIR = O
PORT opb_sdram_0_SDRAM_DQ = opb_sdram_0_SDRAM_DQ, VEC = [0:15], DIR = IO
PORT GPIO_d_out = GPIO_d_out, VEC = [0:1], DIR = O
PORT opb_sdram_0_SDRAM_Init_done = opb_sdram_0_SDRAM_Init_done, DIR = O
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_ALLOW_ICACHE_WR = 1
PARAMETER C_ALLOW_DCACHE_WR = 1
PARAMETER C_CACHE_BYTE_SIZE = 4096
PARAMETER C_DCACHE_BYTE_SIZE = 4096
PARAMETER C_USE_DCACHE = 0
PARAMETER C_USE_ICACHE = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT RESET = sys_rst_s
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT INTERRUPT = opb_intc_0_Irq
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x20600000
PARAMETER C_HIGHADDR = 0x2060ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
PORT Interrupt = RS232_Interrupt
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN opb_sdram
PARAMETER INSTANCE = opb_sdram_0
PARAMETER HW_VER = 1.00.e
PARAMETER C_BASEADDR = 0x86000000
PARAMETER C_HIGHADDR = 0x87ffffff
PARAMETER C_SDRAM_DWIDTH = 16
PARAMETER C_SDRAM_AWIDTH = 13
PARAMETER C_OPB_CLK_PERIOD_PS = 20000
PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 1
PARAMETER C_INCLUDE_BURST_SUPPORT = 1
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_TRAS = 120000
PARAMETER C_SDRAM_TRC = 70000
PARAMETER C_USE_POSEDGE_OUTREGS = 0
PARAMETER C_SDRAM_TCCD = 1
PARAMETER C_SDRAM_CAS_LAT = 2
BUS_INTERFACE SOPB = mb_opb
PORT SDRAM_Clk = opb_sdram_0_SDRAM_Clk
PORT SDRAM_CKE = opb_sdram_0_SDRAM_CKE
PORT SDRAM_CSn = opb_sdram_0_SDRAM_CSn
PORT SDRAM_RASn = opb_sdram_0_SDRAM_RASn
PORT SDRAM_CASn = opb_sdram_0_SDRAM_CASn
PORT SDRAM_WEn = opb_sdram_0_SDRAM_WEn
PORT SDRAM_DQM = opb_sdram_0_SDRAM_DQM
PORT SDRAM_BankAddr = opb_sdram_0_SDRAM_BankAddr
PORT SDRAM_Addr = opb_sdram_0_SDRAM_Addr
PORT SDRAM_DQ = opb_sdram_0_SDRAM_DQ
PORT SDRAM_Init_done = opb_sdram_0_SDRAM_Init_done
PORT OPB_Clk = sys_clk_s
PORT SDRAM_Clk_in = sys_clk_s
END
BEGIN opb_gpio
PARAMETER INSTANCE = opb_gpio_0
PARAMETER HW_VER = 3.01.b
PARAMETER C_IS_BIDIR = 0
PARAMETER C_GPIO_WIDTH = 2
PARAMETER C_DOUT_DEFAULT = 0xffffffff
PARAMETER C_BASEADDR = 0x31000000
PARAMETER C_HIGHADDR = 0x310001ff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT GPIO_d_out = GPIO_d_out
END
BEGIN opb_mdm
PARAMETER INSTANCE = opb_mdm_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x32000000
PARAMETER C_HIGHADDR = 0x3200ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN opb_timer
PARAMETER INSTANCE = opb_timer_0
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x33000000
PARAMETER C_HIGHADDR = 0x330000ff
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = opb_timer_0_Interrupt
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x34000000
PARAMETER C_HIGHADDR = 0x3400001f
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Intr = opb_timer_0_Interrupt & RS232_Interrupt
PORT Irq = opb_intc_0_Irq
END
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