RE: [microblaze-uclinux] why such idiv latency of 34 cycles?

["Goran Bilski" <goran.bilski@xxxxxxxxxx>]

Hi,

Division is a serial algorithm which can not easily be parallelized like multiplication.
32 bit division requires 32 cycles, the 2 extra cycles are added for handling the result sign and the sign of the operands.
Just creating 2 bit of result per clock cycle is a large increase in the complexity of the implementation.

There exists a number of different algorithm for doing division but non is as small as this single-bit implementation.

Göran


-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Brettschneider Falk
Sent: Tuesday, August 23, 2005 11:40
To: microblaze-uclinux@itee.uq.edu.au
Subject: [microblaze-uclinux] why such idiv latency of 34 cycles?

Hi,
please, look at
XilinxEDK6.3i\doc\mb_ref_guide.pdf, Chapter 4 "MicroBlaze Instruction Set
Architecture" where it says:

idiv Integer Divide
	Latency
	2 cycles if (rA) = 0, otherwise 34 cycles

Why is division that slow?
(Most other instructions have latency around 2)

Such slow division gives us big headaches in the algorithm code.

Cheers
Falk
___________________________________

  Falk Brettschneider
  Software Developer
  http://www.baumeroptronic.de
 
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/




___________________________
microblaze-uclinux mailing list
microblaze-uclinux@itee.uq.edu.au
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/