RE: [microblaze-uclinux] why such idiv latency of 34 cycles?

["Goran Bilski" <goran.bilski@xxxxxxxxxx>]

Hi Rudi,

Sure but there are tons of other feature wanted for MicroBlaze.
When I was about to implement the divider, I was thinking of doing a radix-4 SRT algorithm since I done it before. It does 2 bits per clock cycle.
The division would take 18 clock cycles instead of 34. 
However the logic is also much larger and at that time I couldn't justify that.

If anyone has requirements or a wishlist for MicroBlaze, please send them to me. We have internally a long list of things to do but I suspect that we also are missing some stuff. Also if you wish stuff that are further down our list it might be moved up.

Falk, Could you send me some more details on the algorithm?

Göran 

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Rudolf Usselmann
Sent: Tuesday, August 23, 2005 16:08
To: microblaze-uclinux@itee.uq.edu.au
Subject: RE: [microblaze-uclinux] why such idiv latency of 34 cycles?

On Tue, 2005-08-23 at 12:36 +0100, Goran Bilski wrote:
> Hi,
> 
> Division is a serial algorithm which can not easily be parallelized like multiplication.
> 32 bit division requires 32 cycles, the 2 extra cycles are added for handling the result sign and the sign of the operands.
> Just creating 2 bit of result per clock cycle is a large increase in the complexity of the implementation.
> 
> There exists a number of different algorithm for doing division but non is as small as this single-bit implementation.
> 
> Göran

Goeran,

why not give users the option of a single, dual or quad bit(radix)
divider ? The additional logic a two bit divider would add isn't
that much larger ...

Kind Regards,
rudi
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