Re: [microblaze-uclinux] why such idiv latency of 34 cycles?

["e.stiebler" <emu@xxxxxxxxxxx>]

Brettschneider Falk wrote:
> Hi, I'm not sure what you mean.
> Cheers
> F@lk

Find out, where your software/algorithms spents it cycles,
and make a little hardware/controller for it.
Connect it to the microblaze via FSL.

cheers,
emanuel

>>-----Original Message-----
>>From: owner-microblaze-uclinux@itee.uq.edu.au
>>[mailto:owner-microblaze-uclinux@itee.uq.edu.au]On Behalf Of Goran
>>Bilski
>>Sent: Wednesday, August 24, 2005 2:50 PM
>>To: microblaze-uclinux@itee.uq.edu.au
>>Subject: RE: [microblaze-uclinux] why such idiv latency of 34 cycles?
>>
>>
>>Hi Falk,
>>
>>Can some part of the core be extracted and be implemented as 
>>a FSL based SW accelerator?
>>
>>Göran
> 
> 
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