RE: [microblaze-uclinux] Microblaze Performance.

["Goran Bilski" <goran.bilski@xxxxxxxxxx>]

Hi,

I would also enable the barrel shifter since it can have a major impact on some C code. 

Göran

-----Original Message-----
From: owner-microblaze-uclinux@itee.uq.edu.au [mailto:owner-microblaze-uclinux@itee.uq.edu.au] On Behalf Of Pavel Ivanchenko
Sent: Wednesday, September 14, 2005 19:42
To: microblaze-uclinux@itee.uq.edu.au
Subject: Re: [microblaze-uclinux] Microblaze Performance.

Hi.
I not find in your transceiver.c instructions to enable and initializing 
cach (microblaze_enable_icache() etc)
Your use old SDRAM core version  - 1.00.a. Version v1.00.c have burst mode.

----- Original Message ----- 
From: "Abot Botbot" <dejanigma@hotmail.com>
To: <microblaze-uclinux@itee.uq.edu.au>
Sent: Wednesday, September 14, 2005 7:00 PM
Subject: [microblaze-uclinux] Microblaze Performance.


> Hey Folks,
>
>   This is my first post so try not to let my inexperience offend. My
> question relates to the hardware options one uses in setting up the
> microblaze. With EDK and BSB I quickly got a microblaze working. With some
> finagling and an XMD stub I got large, complicated programs running out of
> the external SDRAM (im using the Digilent S3 starter board, or an
> equivalent). But I see a major problem with the performance. Here are the
> numbers and comparissons I am using: The code runs a 64-point FFT on an
> array of data with real and imaginary parts. It is a lot of calculation, 
> so
> it is easy to time. I run 1000 of these in a loop and it takes 
> approximately
> 4 minutes, an unfathomably long amount of time in the world of DSP. The
> comparison is vs a Motorola DSP board which is also doing emulated 
> floating
> point arithmetic, which performs 1000 FFTs in under a second. My theory at
> this point is that I am missing a major design flaw which is inhibiting my
> performance. Technically, the microblaze has a core clock of 100 MHz as 
> well
> as the SDRAM. They are interfaced using the Cache-Link FSL bus and a BRAM
> cache local to the microblaze. With these statistics, there is no real
> reason for it to behave so poorly. Even adding a hardware FPU doesn't 
> change
> the result in the least.
>   Here is what I would like, if anyone would be so kind: A basic rundown 
> of
> the hardware configuration options necissary to optomize microblaze
> performance for running from external memory. There must be a way to make
> the microblaze run in an equivalent way to this outdated 1998 Motorola
> 24-bit DSP chip. If not then Xilinx and IBM have a lot of explaining to 
> do.
> For refference I will supply the relevant design files I have available.
>
> Thanks So Much,
> Andy
>
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