[microblaze-uclinux] FSL 2.0 with Async_clks=1 and depth=1 don't work

[Claudio Lanconelli <lanconelli.claudio@xxxxxxxxx>]

Hi,
It may be off-topic but can prevent other people to loose time against
a bug in FSL.
I used FSL v2.00a in the following configuration, but it doesn't work.

Asynchronous clocks with FSL_S_Clk < FSL_M_Clk and depth = 1

BEGIN fsl_v20
 PARAMETER INSTANCE = iolink_1
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_FSL_DWIDTH = 16
 PARAMETER C_FSL_DEPTH = 1
 PARAMETER C_USE_CONTROL = 0
 PARAMETER C_ASYNC_CLKS = 1
 PARAMETER C_IMPL_STYLE = 0
 PORT SYS_Rst = sys_rst
 PORT FSL_M_Clk = fast_clk
 PORT FSL_S_Clk = slow_clk
END

In my case the slave is microblaze
and the master is the IP core available at http://www.lancos.com/fpga.html.
I simulated the system with ModelSim
and I think I found the problem in fsl_v20.vhd.

Here a snippet of code from fsl_v20.vhd :

      FSL_S_Sync : process (FSL_S_Clk, fsl_rst_i) is
      begin  -- process FSL_S_Sync
        if fsl_rst_i = '1' then         -- asynchronous reset (active high)
          Fsl_s_exists_i <= '0';
        elsif FSL_S_Clk'event and FSL_S_Clk = '1' then  -- rising clock edge
          fifo_write <= FSL_M_Write;    -- <<---------
          if (fifo_write = '1') then    -- <<--------- Look here
            Fsl_s_exists_i <= '1';      -- <<---------
          end if;
          if (FSL_S_Read = '1') then
            Fsl_s_exists_i <= '0';            
          end if;
        end if;
      end process FSL_S_Sync;

If FSL_S_Clk is slower than FSL_M_Clk and the master write one word 
(FSL_M_Write 1 clk long)
fifo_write will never be 1 and so FSL_S_Exists will never raise

   +---+   +---+   +---+   
   |   |   |   |   |   |      FSL_M_Clk
---+   +---+   +---+   +---

           +-------+
           |       |          FSL_M_Write
-----------+       +-------

--+      +------+      +---
  |      |      |      |      FSL_S_Clk
  +------+      +------+   

FSL_S_Exists remains low, and the microblaze hangs waiting for data just 
arrived.

If I change the depth to 16 or use synchronous clocks it works fine.

Regards,
Claudio Lanconelli
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