Paul,Yea the design was compiled in EDK using BSB. I didn't want to get into specifics right away, but I can give you a little perspective. The algorithm I'm using computes a floating point FFT on a 2x64-point array (real, imag). This was originally running on a TI DSP chip, but we want to reduce the form factor and eliminate the a lot of the other hardware with one FPGA. This operation is run as emulated floating point math on the 150 MHz DSP, it does several thousand FFTs per second. On the SP3 and the ML401 designs running the same code (at 50 Mhz and 100 MHz respectively), the same algorithm results in about one FFT per second, on both platforms. Granted we're comparing apples and oranges, but the difference in speed is phenominal, several orders of magnitude. Now that you have a little perspective, maybe you have a better idea where the problem is. The past month has been spent just trying to get around these massive performance hinderances. Adding the FPU didn't give any noticable increase in speed. The designs are running out of external memory (SDRAM) with cachelink over FSL to the microblaze. Granted it takes dozens of clock cycles for every read and write, or at least in the worst cases, but that still doesn't add up to the performance I see. Some people have asked why we are using the mircoblaze for DSP at all, but I don't see any architecture restrictions to doing emulated floating point math at a decent speed. Since the clock speeds are different and the memory access times are longer, I would immedaitely expect to have maybe 10% of the speed of the 150 MHz DSP, but i get .001% or worse... If you need any further info I can go on all day :D.. Any insight you can give would be invaluable. In the final implementation I expect to have dedicated hardware for doing the FFTs, but the microblaze should still be able to do it decently, right?
Thanks, Andy
From: Paul Hartke <phartke@xxxxxxxxxxxx> To: microblaze-uclinux@xxxxxxxxxxxxxx, Abot Botbot <dejanigma@xxxxxxxxxxx> CC: microblaze-uclinux@xxxxxxxxxxxxxx Subject: Re: [microblaze-uclinux] Jtag Debug Date: Wed, 26 Oct 2005 07:53:35 -0700How do you know it runs "slow"--that's really a value judgement? What makesyou think it should run faster--or even slower for that matter? The design appears to be created by Base System Builder which lots of folks have used on ml401. Paul Quoting Abot Botbot <dejanigma@xxxxxxxxxxx>: > Hey Friends, > > This might be considered off topic, but I think I'm missing a > fundamantal > explanation for the performance that I get. Here's my basic design flow, > which doesn't use uCLinux yet, I was just trying to verify that the DSP > functionality I want is possible on the microblaze... I download the XMD > stub to the board, then run "dow executable.elf" from XMD and type > "run"... > This sets my code in motion, but it seems to be going extremely slow. > It's > running entirely out of SRAM, but that shouldn't be the only factor in > the > performance I'm seeing... I'm wondering if my whole system is running > over > the JTAG clock and putting out debug symbols to the PC, even though I'm > not > observing them, and I took the -g option out of the compiler flags.. So > two > questions... Am I running in some debug mode where it is running much > slower> than it could be... How do I get the hardware to run independantly, if it> is > in some debug mode.. After I finish a few things for my graduate classes > (mid terms, blech!) I will get back on the uCLinux train and get that> running on my ML401 board. Thanks for any help you can give! I'll attatch> some files in case anyone thinks looking at them will help them to > understand. > > Thanks, > Andy >
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