Re: [microblaze-uclinux] The one cycle access to LMB

[alucero@xxxxxxxxx]

Hi John,

> Apart from the existing code in mach_early_init, which copies the
> interrupt vectors, there should be no other accesses into LMB.

Ok. I'm a bit confused. I have two bram controllers at my mhs file, one an opb 
interface controller and the other is the LMB interface controller. The 
addresses for the OPB controller are 0x0 to 0x00001fff, meanwhile the 
addresses for LMB are 0x20000000-0x20001fff. I was using the LMB addresess to 
copy the irq routine (just the irq entry at entry.S, not specific irq devices 
routines since what I want is to measure the worst interrupt latency case).
However, I have seen that the addresses you use to copy the interrupt and 
exception table is the 0x0, in my case the OPB bram controller address. 
Is that right? Is there a conflict in my configuration file?

I attach my mhs file.

> If you are using XMD/MDM, try setting a HW write breakpoint at one of
> the corrupted addresses, and set the kernel running.  You might be able
> to trap the offending instruction this way.

Ohh. I did not know the XMD had this option. GREAT!

I want to release my work the next weeks, and I think it could be interesting 
for the microblaze comunity ... real time?.

> Regards,
>
> John
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-- 
Alejandro Lucero
OS3, OS Serveis i Solucions
www.os3sl.com
Ingeniería Informática
+34 665687168
Av.Benjamin Franklin
CEEI. Parque Tecnológico de Paterna
Valencia(Spain)

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