Hi, Andy,
The XMD connection problem is due to the
special JTAG arrangement in V4LX25 ES device (Engineering Sample device) on your
ML401 board. Following two settings are needed to make XMD connection
work.
(1) opb_mdm 2.01a version
(2) In your project/etc directory , try to
edit the file xmd_microblaze_0.opt, (this file is auto generated when you launch
XMD first time)
change to : connect mb mdm
-cable type xilinx_parallel port LPT1 frequency 5000000 -bscan USER1 -debugdevice cpunr 1
You could
not be able to use chipscope and XMD at the same time with the ES device. Only
one of them could be used...
Hope this will be helpful.
Kevin
-----Original Message-----
From:
owner-microblaze-uclinux@xxxxxxxxxxxxxx [mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx]
On Behalf Of Abot Botbot
Sent: Friday, November 18, 2005 1:58 AM
To:
microblaze-uclinux@xxxxxxxxxxxxxx
Subject: RE: [microblaze-uclinux] Jtag
Debug
Folks,
I was trying to work with a non-rtos
microblaze design which I had received from Kevin Chen, who is on this list. He
helped me take the FFT code I was using and increase its performance. When I
first got his project files a few weeks ago everything worked fine. Now when I
try and connect to the microblaze via XMD to download my bit stream I see the
output shown in the .jpg I attached to this email. I've never seen this output
before. Other projects <i>seem</i> to work correctly but XMD over my
USB programmer is buggy sometimes failing, sometimes not validating the boundary
scan chain, sometimes not working at all. Does it sound possible that I have a
bad USB programmer? The only reason I ask is that a week ago this computer I'm
using trashed a USB hard drive enclosure. Didn't kill the drive, but the
enclosure is totally shot.. DAMN DELLS! Anyway, has anyone seen this error
before? The system looks fine in EDK, all my options look normal for XMD debug
and whatnot. I'm using EDK 7.12 and ISE 7.1, latest and greatest I think, ML401
board. Any help on this matter would be much
appreciated.
Thanks,
Andy
>From: "Kevin Chen"
<kevin.chen@xxxxxxxxxx>
>Reply-To:
microblaze-uclinux@xxxxxxxxxxxxxx
>To:
<microblaze-uclinux@xxxxxxxxxxxxxx>
>Subject: RE:
[microblaze-uclinux] Jtag Debug
>Date: Thu, 3 Nov 2005 09:51:02
+0800
>
>Andy,
>
>I've created a simple hardware
version, only microblaze, uart and
>mch_opb_ddr included. The implemention
time is great reduced to be
>about several minutes. There are also some
change for the software.
>The overall run time is as expected,
winthin second... I am not sure if
>the result is correct. Hope this will
help...
>
>If you'd like the design, send me email
offline.
>
>Thanks
>-Kevin
>
>Detail:
>
>Hardware:
>
mch_opb_ddr (32 bit DDR, 64MB total)
> opb_uart
(115200 8-N-1 )
> microblaze (FPU, hard_multiplier
enabled)
> BRAM
(64KB)
>
>Software:
> - remove math.h
file
> - change all double to float, remove
timer/interrupt codes, add
>cache enable in
transceiver.c
> - copy
$EDK_INSTALL\gnu\microblaze\nt\microblaze\lib\libm_m_fps.a
>to your
project microblaze_0\lib and rename to libm.a. this will
>ensure
single precision library is used.
> - Software are
compiled at DDR
>
>Execution:
> - EDK
7.1.2, ISE 7.1.3
> - Download
hardware
> - Launch
XMD
> - command: dow
fft/executable.elf
> - command:
run
>
>
>
>
>
>
>
>
>
>-----Original
Message-----
>From: owner-microblaze-uclinux@xxxxxxxxxxxxxx
>[mailto:owner-microblaze-uclinux@xxxxxxxxxxxxxx]
On Behalf Of Abot
>Botbot
>Sent: Friday, October 28, 2005 9:45
PM
>To: microblaze-uclinux@xxxxxxxxxxxxxx
>Subject: Re:
[microblaze-uclinux] Jtag Debug
>
>Hey
all,
>
> Kevin asked for the project file, so here
it is.. Hope you got a
>few hours to compile it
:*(
>
>Thanks,
>Andy
>
>
> >From: John
Williams <jwilliams@xxxxxxxxxxxxxx>
> >Reply-To:
microblaze-uclinux@xxxxxxxxxxxxxx
> >To:
microblaze-uclinux@xxxxxxxxxxxxxx
> >Subject: Re: [microblaze-uclinux]
Jtag Debug
> >Date: Fri, 28 Oct 2005 08:42:30 +1000
>
>
> >Hi Andy,
> >
> >A couple of
comments/observations about your system, that may be
>relevant.
>
>
> >From your MHS file:
> >
> >BEGIN
mch_opb_ddr
> > PARAMETER INSTANCE = DDR_SDRAM_64Mx32
>
> PARAMETER HW_VER = 1.00.a
> >
> >
>
>[snip]
> >
> > PARAMETER C_DDR_AWIDTH = 13
>
>
> >You have no PARAMETER C_DDR_DWIDTH set - by default it is 16
(look at
> >MPD file), but the name of your peripheral suggests that
you have
> >32-bit wide DDR.
> >
> >
>
> [snip]
> >
> > BUS_INTERFACE SOPB =
mb_opb
> > BUS_INTERFACE MCH0 = ixcl
> >
BUS_INTERFACE MCH1 = dxcl
> >
> >I am surprised your system
works at all - there is a bug in the
> >opb_mch_ddr controller - I
reported the bug to Xilinx a while ago,
> >and understand that a patch
shhould be released soon.
> >
> >In the systems where I saw
the bug (66 MHz w/ 16 bit wide DDR) the
> >XCL interface would lock up
the CPU - but maybe in your system it's
> >manifesting itself as very
slow instruction fetch?
> >
> >I can say with some certainty
that the debug/MDM controller is not
> >the cause of your performance
woes.
> >
> >Try the OPB_DDR controller instead (with caches
of course), see if
> >that
>
> >has any impact. In
principle, the MCH controllers are much faster,
> >but
>
>
>until the bug in the mch_opb_ddr is fixed, you probably shouldn't
try
> >to use it.
> >
> >Cheers,
> >
>
>John
> >
> >
> >
> >Abot Botbot
wrote:
> > > Hey Friends,
> > >
> >
> This might be considered off topic, but I think I'm missing
a
> > > fundamantal explanation for the performance that I get.
Here's my
> > > basic design flow, which doesn't use uCLinux yet, I
was just
> > > trying to verify that the DSP functionality I want is
possible on
> > > the microblaze... I download the XMD stub to the
board, then run
> > > "dow executable.elf" from XMD and type
"run"... This sets my code
> > > in motion, but it seems to be going
extremely slow. It's running
> > > entirely out of SRAM, but that
shouldn't be the only factor in the
> > > performance I'm seeing...
I'm wondering if my whole system is
> > > running over the JTAG
clock and putting out debug symbols to the
> > > PC,
>
>
> > even though I'm not observing them, and I took the -g option
out
> > > of the compiler flags.. So two questions... Am I running
in some
> > > debug mode where it is running much slower than it
could be... How
> > > do I get the hardware to run independantly, if
it is in some debug mode..
>
> > > After I finish a few things
for my graduate classes (mid terms,
> > > blech!) I will get back on
the uCLinux train and get that running
> > > on
>
> >
> my ML401 board. Thanks for any help you can give! I'll attatch
> >
> some files in case anyone thinks looking at them will help them to
>
>understand.
> > >
> > > Thanks,
> > >
Andy
> > >
> > >
_________________________________________________________________
> >
> Express yourself instantly with MSN Messenger! Download today -
>
> > it's
>
> > > FREE!
> > > http://messenger.msn.click-url.com/go/onm00200471ave/direct/01/
>
> >
> > >
/*****************************************************************
> >
> **
> > > *
> > > * CAUTION: This file is
automatically generated by libgen.
> > > * Version: Xilinx EDK 7.1.2
EDK_H.12.5.1
> > > * DO NOT EDIT.
> > > *
> >
> * Copyright (c) 2005 Xilinx, Inc. All rights reserved.
> >
> *
> > > * Description: Driver parameters
> > >
*
> > >
******************************************************************
> >
> */
> > >
> > > #define STDIN_BASEADDRESS 0x40600000
#define STDOUT_BASEADDRESS
> > > 0x40600000
> >
>
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_DLMB_CNTLR_BASEADDR
0x00000000 #define
> > > XPAR_DLMB_CNTLR_HIGHADDR 0x00001FFF
#define
> > > XPAR_ILMB_CNTLR_BASEADDR
>
> > >
0x00000000 #define XPAR_ILMB_CNTLR_HIGHADDR 0x00001FFF
> > >
>
> >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_XUARTLITE_NUM_INSTANCES
2 #define
> > > XPAR_DEBUG_MODULE_BASEADDR 0x41400000
#define
> > > XPAR_DEBUG_MODULE_HIGHADDR 0x4140FFFF #define
>
> > XPAR_DEBUG_MODULE_DEVICE_ID 0 #define XPAR_DEBUG_MODULE_BAUDRATE
0
> > > #define XPAR_DEBUG_MODULE_USE_PARITY 0 #define
> >
> XPAR_DEBUG_MODULE_ODD_PARITY 0 #define XPAR_DEBUG_MODULE_DATA_BITS
>
> > 0
>
> > > #define XPAR_RS232_UART_BASEADDR
0x40600000 #define
> > > XPAR_RS232_UART_HIGHADDR 0x4060FFFF
#define
> > > XPAR_RS232_UART_DEVICE_ID 1 #define
XPAR_RS232_UART_BAUDRATE 9600
> > > #define
XPAR_RS232_UART_USE_PARITY 0 #define
> > >
XPAR_RS232_UART_ODD_PARITY 0 #define XPAR_RS232_UART_DATA_BITS 8
> >
>
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_XGPIO_NUM_INSTANCES 4
#define XPAR_LEDS_4BIT_BASEADDR
> > > 0x40040000 #define
XPAR_LEDS_4BIT_HIGHADDR 0x4004FFFF #define
> > >
XPAR_LEDS_4BIT_DEVICE_ID 0 #define
> > >
XPAR_LEDS_4BIT_INTERRUPT_PRESENT 0 #define XPAR_LEDS_4BIT_IS_DUAL
> >
> 0 #define XPAR_LEDS_POSITIONS_BASEADDR 0x40020000 #define
> > >
XPAR_LEDS_POSITIONS_HIGHADDR 0x4002FFFF #define
> > >
XPAR_LEDS_POSITIONS_DEVICE_ID 1 #define
> > >
XPAR_LEDS_POSITIONS_INTERRUPT_PRESENT 0 #define
> > >
XPAR_LEDS_POSITIONS_IS_DUAL 0 #define
> > >
XPAR_PUSH_BUTTONS_POSITION_BASEADDR 0x40000000 #define
> > >
XPAR_PUSH_BUTTONS_POSITION_HIGHADDR 0x4000FFFF #define
> > >
XPAR_PUSH_BUTTONS_POSITION_DEVICE_ID 2 #define
> > >
XPAR_PUSH_BUTTONS_POSITION_INTERRUPT_PRESENT 0 #define
> > >
XPAR_PUSH_BUTTONS_POSITION_IS_DUAL 0 #define
> > >
XPAR_DIP_SWITCHES_8BIT_BASEADDR 0x40060000 #define
> > >
XPAR_DIP_SWITCHES_8BIT_HIGHADDR 0x4006FFFF #define
> > >
XPAR_DIP_SWITCHES_8BIT_DEVICE_ID 3 #define
> > >
XPAR_DIP_SWITCHES_8BIT_INTERRUPT_PRESENT 0 #define
> > >
XPAR_DIP_SWITCHES_8BIT_IS_DUAL 0
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_XIIC_NUM_INSTANCES
1
> > > #define XPAR_IIC_EEPROM_BASEADDR 0x40800000 #define
>
> > XPAR_IIC_EEPROM_HIGHADDR 0x4080FFFF #define
> > >
XPAR_IIC_EEPROM_DEVICE_ID 0 #define XPAR_IIC_EEPROM_TEN_BIT_ADR 0
> >
> #define XPAR_IIC_EEPROM_GPO_WIDTH 1
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_XSYSACE_MEM_WIDTH
16
> > > #define XPAR_XSYSACE_NUM_INSTANCES 1 #define
> >
> XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x41800000 #define
> > >
XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x4180FFFF #define
> > >
XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0 #define
> > >
XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define
XPAR_DDR_SDRAM_64MX32_MEM0_BASEADDR 0x24000000 #define
> > >
XPAR_DDR_SDRAM_64MX32_MEM0_HIGHADDR 0x27FFFFFF
> > >
> >
> /*****************************************************************
>
> > */
> > >
> > > #define
XPAR_XEMAC_NUM_INSTANCES 1 #define
> > > XPAR_ETHERNET_MAC_BASEADDR
0x40C00000 #define
> > > XPAR_ETHERNET_MAC_HIGHADDR 0x40C0FFFF
#define
> > > XPAR_ETHERNET_MAC_DEVICE_ID 0 #define
> >
> XPAR_ETHERNET_MAC_ERR_COUNT_EXIST 1 #define
> > >
XPAR_ETHERNET_MAC_DMA_PRESENT 1 #define
> > >
XPAR_ETHERNET_MAC_MII_EXIST
> > > 1 #define
XPAR_ETHERNET_MAC_CAM_EXIST 0 #define
> > >
XPAR_ETHERNET_MAC_JUMBO_EXIST 0
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define
XPAR_SRAM_256KX32_NUM_BANKS_MEM 1
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define
XPAR_SRAM_256KX32_MEM0_BASEADDR 0x22000000 #define
> > >
XPAR_SRAM_256KX32_MEM0_HIGHADDR 0x220FFFFF
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_XTMRCTR_NUM_INSTANCES 1
#define
> > > XPAR_OPB_TIMER_1_BASEADDR 0x41C00000 #define
>
> > XPAR_OPB_TIMER_1_HIGHADDR 0x41C0FFFF #define
> > >
XPAR_OPB_TIMER_1_DEVICE_ID 0
> > >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define
XPAR_INTC_MAX_NUM_INTR_INPUTS 1 #define XPAR_XINTC_HAS_IPR
> > >
1
>
> > > #define XPAR_XINTC_USE_DCR 0 #define
XPAR_XINTC_NUM_INSTANCES 1
> > > #define XPAR_OPB_INTC_0_BASEADDR
0x41200000 #define
> > > XPAR_OPB_INTC_0_HIGHADDR 0x4120FFFF
#define
> > > XPAR_OPB_INTC_0_DEVICE_ID 0 #define
XPAR_OPB_INTC_0_KIND_OF_INTR
> > > 0x00000000
> >
>
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_INTC_SINGLE_BASEADDR
0x41200000 #define
> > > XPAR_INTC_SINGLE_HIGHADDR 0x4120FFFF
#define
> > > XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define
> > > XPAR_OPB_TIMER_1_INTERRUPT_MASK 0X000001
#define
> > > XPAR_OPB_INTC_0_OPB_TIMER_1_INTERRUPT_INTR 0
>
> >
> > >
/*****************************************************************
> >
> */
> > >
> > > #define XPAR_CPU_CORE_CLOCK_FREQ_HZ
100000000
> > >
> > >
/*****************************************************************
> >
> */
> > >
> >
> >
> >--
>
>Dr John Williams, Research Fellow,
> >Embedded Systems Group /
Reconfigurable Computing School of ITEE, The
> >University of
Queensland, Brisbane, Australia
> >(p) +61 7 33652185 (f) +61 7
33654999 (m) +61 403969243
> >___________________________
microblaze-uclinux mailing list
>
>microblaze-uclinux@xxxxxxxxxxxxxx
> >Project Home Page :
>
>http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
>
>Mailing List Archive :
> >http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
>
>
>
>_________________________________________________________________
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