Re: [microblaze-uclinux] Multi-channel OPB DDR Memory Controller

[John Williams <jwilliams@xxxxxxxxxxxxxx>]

Abot Botbot wrote:
> Hey Folks,
>
>  Just got an email from Xilinx about their "new" features for embedded 
> processors including :
>
> Multi-channel OPB DDR Memory Controller
> Tri-Mode Ethernet MAC
>
>  does the multi-channel controller make multiple microblaze designs more 
> pheasable from a single physical memory? Just thought I'd throw this 
> out. I'm sure you are all in the know already anyway :D


The multichannel mem controller just makes multi-cpu systems more 
efficient - instead of fighting on the OPB bus for memory bandwidth 
(with all other system peripherals), the CPUs instead fight "inside" the 
memory controller for bandwidth.

So, it's still a bandwidth fight but there are fewer players!

Also, the mch_opb_ddr controller is limited to 4 ports (each CPU 
requires 2 ports) - so you are stuck with max 2 cpus on a single memory.

Some benchmarks I've done on multi-microblaze (and multi-linux) systems 
using the mch_opb_ddr controller show that memory contention causes 
performance impacts of up to 35% on each CPU - quite high, but still 
much better than if they were both on the OPB bus.

Using the mch_opb_ddr for a single CPU, vs the opb_ddr, in an mb-uclinux 
system, gives an instant 2X speedup in real terms, due to the more 
efficient cache fetch architecture (CacheLink)

Regards,

John
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