You need the phase shift in there:
http://www.xilinx.com/products/boards/ml310/current/index.html
http://www.xilinx.com/products/boards/ml310/current/reference_designs/base/ml310_base_ucf_update.zip
Looks like xilinx has not updated the BSB files to automatically include
it.
Paul
Quoting elynum@xxxxxxx:
Yes, I updated to the service pack 2 package and stripped out everything
except for the uart and the ddr controller and the sram memory test just
hangs. Here's a copy of my mhs, mss and ucf files.
>
> From: Paul Hartke <phartke@xxxxxxxxxxxx>
> Date: 2006/01/11 Wed AM 11:27:19 EST
> To: microblaze-uclinux@xxxxxxxxxxxxxx, elynum@xxxxxxx
> CC: microblaze-uclinux@xxxxxxxxxxxxxx
> Subject: Re: [microblaze-uclinux] ml310 development board sram failure
>
> I've successfully used Base System Builder created designs with the DDR
on
> ml310. I presume you are using the latest EDK/ISE Service Packs?
>
> Paul
>
> Quoting elynum@xxxxxxx:
> > Hello, does anyone have the ml310 development board from xilinx?
Well,
> > I'm having a problem with the ddr sdram. I had this same problem
with
> > another development board from avnet. The memory test for the DDR
SDRAM
> > fails. Now avnet offered the solution in their file that dummy
signals
> > had to be created because the fpga was taking a voltage down. That
> > solved that issue but for this ml310 board I'm having the same
problem is
> > that the SDRAM is failing the memory test but the dummy signal
solution I
> > don't think works for this board because it has been laid out
> > differently. Has someone encountered this problem with the ML310 dev
> > system.
> >
>
___________________________
microblaze-uclinux mailing list
microblaze-uclinux@xxxxxxxxxxxxxx
Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux
Mailing List Archive :
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/
--
No virus found in this incoming message.
Checked by AVG Free Edition.
Version: 7.1.371 / Virus Database: 267.14.17/227 - Release Date: 11.1.2006